Security Issues in QCA Circuit Design - Power Analysis Attacks - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 208

By using the majority logic reduction method [ 43 ], the above expressions can
be further minimized by the following logic reduction expressions:

y 1 : x 3 x 1 + x 3 x 1 x 2
= M ( M ( x 3 , 0 , x 1 ) ,

M ( x 3 , 1 , x 1 ) ,M ( x 3 , 1 , x 2 )) .

(15)

y 2 : x 4 ( x 3 x 1 + x 3 x 1 )+ x 4 ( x 3 x 2 x 1 )
= M ( M (( x 3 x 1 + x 3 x 1 ) , 0 , x 4 ) , 1 ,M ( x 4 , 0 , ( x 3 x 2 x 1 ))) . (16)

y 3 : x 2 x 1 + x 2 x 1 x 3
= M ( M ( x 2 , 0 , x 1 ) ,

M ( x 2 , 1 , x 1 ) ,M ( x 2 , 1 ,x 3 )) ,

(17)

( x 1 x 2 + x 2 x 3 + x 1 x 2 x 3 )
= M ( M ( x 1 , 1 , x 2 ) ,

M ( x 2 , 1 , x 3 ) ,M ( x 1 , x 2 , x 3 )) .

(18)

The majority gate based schematic of the Serpent sub-module is shown in Fig. 13 .
By integrating the XOR gates and S 0 -box, the QCA design of the Serpent
sub-module has been implemented in QCADesigner with appropriately assigned
clocking zones as shown in Fig. 14 (different shades indicate the different clock-
ing zones). The design has been checked with QCAPro, which verified that the
outputs are correct for all given inputs.
A QCA design of the Serpent S 0 -box based on majority logic was previously
proposed [ 44 ]. In that design, each term of the logic expressions is implemented
by AND and OR gates which are directly mapped from the CMOS design.
However, since majority based logic reduction was not applied, the design incurs
a much higher cell count and delay [ 45 ]. A comparison between the previous
work and this design is presented in Table 5 . In terms of area, the QCA cell size
used in both designs is 18 nm with a centre-to-centre cell distance of 20 nm. It
can be seen from the comparison table that a much more ecient design of the
Serpent S 0 -box is achieved in this work, with a reduction of 45 %, 42 % and 59 %
in terms of the number of cells, area and latency, respectively.

Table 5. Comparison of two designs of the Serpent S 0 -box

Compared items Previous design [ 44 ] This design Improvement (%)

Complexity 3965 cells 2186 cells 45

5.75 µ m 2 3.35 µ m 2

Area 42

Latency 8 cycles 3.25 cycles 59

4 Power Analysis Attack of QCA Circuits

Differential Power Analysis (DPA) [ 25 ] is the most effective power analysis
attack. DPA attacks do not require a detailed knowledge of the target device
or the circuit architecture. The adversary does not need to know when a par-
ticular operation is actually computed by the cryptographic circuit. Power data