STT-Based Non-Volatile Logic-in-Memory Framework - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 189

energy and 81 . 25 % savings in area over the standard AND-OR implementation
of the 2-input exclusive-OR in the logic-in-memory architecture.
Finally, Fig. 9 provides an estimate of the energy savings in some datapath
components when executed in standard STT-based logic-in-memory mode and
in logic partitioning mode over traditional NML.
6 Conclusion
In this chapter we have discussed a logic-in-memory architecture that is an inte-
gration of two different technologies, STT-MRAM and NML. With clock as con-
trol, the architecture switches between logic and memory mode of operations.
The computation in the architecture is NML style using the magnetostatic cou-
pling between the multilayer STT-MRAM cells. The writing and reading from
the logic is STT-MRAM style using CMOS assisted spin transfer torque and
magnetoresistance of their cells. This unique integration between the two tech-
nologies gives a logic platform that is non-volatile like NML but has a much lower
power consumption and better user interface. Finally, we have shown a Shannon
based logic partitioning between the magnetic plane and the CMOS plane of the
architecture that provides significant performance boost to datapath elements
like exclusive-OR in the architecture.
Acknowledgement. This work is partially supported by NSF Career Award CCF
(0639624), NSF EMT/Nano CCF (0824838), NSF CRI (0551621) and USF Presidential
Doctoral Fellowship.
References
1. Frank, D.J., Dennard, R.H., Nowak, E., Solomon, P.M., Taur, Y., Wong, H.-S.P.:
Device scaling limits of Si MOSFET's and their application dependencies. Proc.
IEEE 89 (3), 259-288 (2001)
2. Slonczewski, J.C.: Current-driven excitation of magnetic multilayers. J. Magn.
Magn. Mater. 159 (1), L1-L7 (1996)
3. Parkin, S.S., Kaiser, C., Panchula, A., Rice, P.M., Hughes, B., Samant, M., Yang,
S.-H.: Giant tunnelling magnetoresistance at room temperature with MgO (100)
tunnel barriers. Nat. Mater. 3 (12), 862-867 (2004)
4. http://www.everspin.com/
5. Cowburn, R., Welland, M.: Room temperature magnetic quantum cellular
automata. Science 287 (5457), 1466-1468 (2000)
6. Imre, A., Csaba, G., Ji, L., Orlov, A., Bernstein, G.H., Porod, W.: Majority logic
gate for magnetic quantum-dot cellular automata. Science 311 (5758), 205-208
(2006)
7. Salahuddin, S.: Current induced switching of ferromagnets for low-power memory
applications. In: ISQED Symposium, Tutorial (2011)
8. Zhu, J.-G.J., Park, C.: Magnetic tunnel junctions. Mater. Today 9 (11), 36-45
(2006)