STT-Based Non-Volatile Logic-in-Memory Framework - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 187

BL 1 BL 2 BL 3

WL

X 1 X 3 X 2

SL 1 SL 2 SL 3

Transistor Transistor

Fig. 8. Cell layout for 2-input exclusive-OR executed through logic partitioning.

5.1 Execution Principle for the 2-Input Exclusive-OR

The 2-input exclusive-OR is evaluated on the basis of the following logical
deductions:

1. When x 1 =1, x 1 ⊕ x 2 = x ₓ 2 ;
2. When x 1 =0, x 1 ⊕ x 2 = x 2 .

The cell layout for the 2-input exclusive-OR is shown in Fig. 8 . The logic
execution takes place in the following four phases.
Phase I: The cofactors x 2 and x ₓ 2 are written into cells X 1 and X 2 respectively.
Phase II: X 3 is clocked followed by clocking X 1 (if x 1 =1)or X 2 (if x 1 = 0).
Phase III: X 3 is released. The cell that was not clocked in Phase II, now acts as
adriverfor X 3 . It eventually takes the value of X 2 = x ₓ 2 (if x 1 =1)or X 1 = x 2
(if x 1 = 0).
Phase IV: All clocked cells are released, i.e. X 1 (if x 1 =1)and X 2 (if x 1 = 0).
The algorithm for the logic partitioning based 2-input exclusive-OR execution
is provided in Algorithm 2 .

5.2 Performance Analysis

We will investigate the cost of execution of the 2-input exclusive-OR by logic par-
titioning (Fig. 8 ) in terms of overall (i) area/cell count; (ii) delay; and
(iii) energy and compare it to the standard mode of execution in the STT-based
non-volatile logic-in-memory framework (Fig. 6 ).

Area/cell count: The total cell count of the logic is three (see Fig. 8 ). This is
75 % less than the sixteen cell standard 2-input exclusive-OR (see Fig. 6 ).
Delay: With logic partitioning, it takes ( t w + t clk + t s ) to generate the output.
t w is the MTJ writing time (Phase I), t clk is the clocking time for the MTJ
(Phase II) and t s is the time for the MTJ to settle after the clock is released
(Phase III). In the standard mode of operation, the time to compute the output
is ( t w +3 t clk + t s ) (see Sect. 4.4 ). Logic partitioning therefore gives us a reduced
delay of 2 t clk .
Energy: With logic partitioning, the total energy required for computation is
(2 I w t w +2 I clk t clk ) V dd where, I w and I clk are the writing and clocking current