STT-Based Non-Volatile Logic-in-Memory Framework - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 185

(iv) Time zone 4 : Duration t clk , when the cell X 13 is clocked and the cells X 11
and X 12 are released.
(v) Time zone 5 : Duration t s , when the cell X 13 is released.

The total time to compute the output at X 13 is therefore t w +3 t clk + t s .

4.5 Performance Analysis

To judge the performance of this architecture we will compare it to NML. As
we discussed in Sect. 3 , NML uses single layer single domain nanomagnets and
their magnetostatic interaction to compute. It is non-volatile with zero leakage.
However, as we mentioned, its main concerns are high power, non-scalability of
write and clock current, lack of CMOS interface for read and write and lack
of control over individual nanomagnets during computing. To alleviate these
concerns, we have used magnetostatic coupling between multilayer STT-MRAM
cells and STT current to realize the non-volatile logic-in-memory architecture.
CMOS integrability in the architecture allows control over 2 2 array of cells.

STT based write and clock used in the architecture are low power, scalable and
CMOS driven when compared to field induced write and clock in NML. Finally,
MR based reading practiced in the architecture is both low power and CMOS
driven that can be integrated on-chip. Table 2 provides the necessary comparison.
From the data, we can safely conclude that

×

1. the architecture has low power write, clock and read mechanisms;
2. it has more control over individual MTJs in logic than was possible in NML;
and
3. it provides electrical interface with the logic through CMOS peripherals.

We will next see how the architecture can very interestingly share logic
responsibility between its magnetic and CMOS plane for improved delay, energy
and area performance.

5 Logic Partitioning

Till now we have seen the magnetic plane in the architecture to do the main
computation. The role of the CMOS plane was to take care of the resource
management for the magnetic plane. In this section we will see how to give some
additional responsibility to the CMOS plane, in order to execute more eciently
while still enjoying the non-volatile property of the magnetic plane. We have
named it “the logic partitioning”. To do this partitioning, we will be taking the
help of the well-known Shannon expansion of logic function. For better under-
standing, we will take the help of a 2-input exclusive-OR to explain the partition-
ing. Also, 2-input exclusive-OR is a fundamental component to any arithmetic
and logical operation. This concept of logic partitioning can be extended for any
n -input logic function as well [ 36 , 37 ].