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STT-Based Non-Volatile Logic-in-Memory
Framework
B
Jayita Das 1(
) , Syed M. Alam 2 , and Sanjukta Bhanja 1
1 University of South Florida, Tampa, FL, USA
jayitadas@mail.usf.edu, bhanja@usf.edu
2 Everspin Technologies Inc., Austin, TX, USA
salam@alum.mit.edu
Abstract. This work describes an integration of logic within the Spin
Transfer Torque Magnetoresistive RAM (STT-MRAM) framework. For
memory, a minimum separation between the cells is required to ensure
bit-to-bit independency. For logic that relies on magnetostatic coupling, a
maximum separation is allowed between magnetic cells for effective com-
putation. Integration of the two functionalities therefore requires meeting
the orthogonal spatial needs of separation. In this work the technological
challenges of this integration are first described followed by the spec-
ifications of the new STT-MRAM based logic-in-memory architecture.
How a spin transfer torque based control, also called clock, can tune
the architecture between logic and memory modes is next described.
A reference free variability tolerant differential read scheme leveraging
the integration is presented. This logic-in-memory framework is also an
integration between magnetic and CMOS planes. Finally, a logic parti-
tioning between the two planes is described that can significantly improve
the performance metrics.
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Keywords: Spin transfer torque
MRAM
MTJ
NML
STT clock
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Logic partitioning
Differential read
Variability tolerant
1
Introduction
For long, the semiconductor industry has relied on Dennard scaling and Moore's
law to meet the ever increasing demands of the user. However, the downside
of scaling (mainly leakage) has started becoming more apparent in newer tech-
nologies [ 1 ]. Therefore, it would not be long before the limits of application-
specific power dissipation would end the benefits of scaling. The solution lies in
alternative technologies to fulfill application specific demands. Two such post-
CMOS technologies are the spin transfer torque magnetoresistive RAM (STT-
MRAM) [ 2 , 3 ] used in building modern non-volatile memories and nanomagnetic
logic (NML) used in building non-volatile zero leakage radiation hard logic. We
will discuss further details of STT-MRAM in Sect. 2 and NML in Sect. 3 .
Compared to CMOS memories like SRAM, STT-MRAM has a lower read
latency. Its footprint is also smaller than DRAM. Unlike modern non-volatile
 
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