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1100, 1110, 1111, 0111, 0011, 0001. The test mode of the reversible Johnson
counter can be designed similar to the reversible ring counter as explained in the
above section.
Similar design methodologies can be proposed based on the example study
shown for testable reversible latches, flip-flops and counters to design other
complex sequential circuits such as shift registers, memory based on proposed
testable D flip-flop and reversible data path functional units.
7 Application of Two Vectors, All 0s and All 1s, Testing
Approach to QCA Computing
QCA computing provides a promising technology to implement reversible logic
gates. The QCA design of Fredkin gate is shown in Fig. 17 using the four-phase
clocking scheme, in which the clocking zone is shown by the number next to z
(z0 means clock 0 zone, z1 means clock 1 zone and so on). It can be seen that the
Fredkin gate has two level majority voter (MV) implementation, and it requires
6 MVs and 4 clocking zones for implementation. The number of clocking zones in
a QCA circuit represents the delay of the circuit (delay between the inputs and
the outputs). Higher the number of clocking zones, lower the operating speed of
the circuit [ 37 ].
Fig. 17. QCA Design of Fredkin Gate using the four-phase clocking scheme, in which
the clocking zone is shown by the number next to z (z0 means clock 0 zone, z1 means
clock 1 zone and so on)
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