Reversible Logic Based Design and Test of Field Coupled Nanocomputing Circuits - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 145

(a) Fredkin gate based testable reversible master-slave D flip-flop
(b) Fredkin gate based testable reversible master-slave T flip-flop
Fig. 11. Fredkin gate based testable reversible master-slave flip-flops
In the test mode:
1. to make the design testable with all 0s input vectors for any stuck-at-1 fault,
the values of the control signals will be mC1 = 0 and mC2 = 0, sC1 = 0 and
sC2 = 0. This will produce the outputs mT1 and sT1 as 0 which results in
disrupting the feedback and the design becomes testable with all 0s input
vectors for any stuck-at-1 fault.
2. to make the design testable with all 1s input vectors for any stuck-at-0 fault,
the values of the control signals will be mC1 = 1 and mC2 = 1, sC1 = 1 and
sC2 = 1. This will result in outputs mT1 and st1 to have the value of 1,
disrupting the feedback, and resulting in the design testable with all 1s input
vectors for any stuck-at-0 fault.
The other type of master-slave flip-flops such as the testable master-slave T
flip-flop, testable master-slave JK flip-flop and testable master-slave SR flip-flop
can be designed similarly in which master is designed using the positive enable
corresponding latch, while the slave is designed using the negative enable Fredkin
gate based D latch. For example, as illustrated in Fig. 11 (b), in the design of