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Fig. 6. Information flow in a QCA wire
computing at logical level. In [ 78 ], a new fault model called crosspoint fault
model is proposed along with the ATPG method. In [ 54 ], a universal test set is
proposed for detection of missing-gate faults in reversible circuits. In [ 8 ], a DFT
methodology for detecting bridging faults in reversible logic circuits is proposed.
Recently, the design of reversible finite field arithmetic circuits with error detec-
tion is also proposed [ 41 ]. An online testing methodology for reversible circuits
using a combination of R1 gate along with R2 gate (a 4*4 Feynman Gate) is pro-
posed in [ 72 ] while in [ 39 ] an automatic conversion of any given reversible circuit
into an online testable circuit that can detect online the single-bit errors, includ-
ing soft errors in the logic blocks is presented. The online testing methodology of
reversible logic circuits is also addressed in [ 14 ]. In our recent work we addressed
the concurrent testing of single missing faults in QCA circuits based on reversible
logic [ 65 , 66 ]. With respect to the work on design of reversible sequential circuits,
various interesting contributions are made in which the designs are optimized
in terms of various parameters such as the number of reversible gates, garbage
outputs, quantum cost, delay etc. [ 11 , 18 , 39 , 43 , 57 , 67 , 69 ].
To the best of our knowledge the oine testing of faults in reversible sequen-
tial circuits is not addressed in the literature. In this work, we present the designs
of reversible sequential circuits that can be tested by using only two test vectors,
all 0s and all 1s for any unidirectional stuck-at-faults. Further, the approach
of fault testing based on conservative logic is extended towards the design of
non-reversible sequential circuits based on a new conservative logic gate called
multiplexer conservative QCA gate (Mx-cqca).
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