Reversible Logic Based Design and Test of Field Coupled Nanocomputing Circuits - Field-Coupled Nanocomputing: Paradigms, Progress, and Perspectives - page 137

(a) QCA 4 Dots (b) QCA cell working as logic '1' and logic '0'

Fig. 2. QCA cell and logic operation

are of two types (i) Binary wire, (ii) Inverter chain. The electrons in adjacent
QCA cells interact with each other resulting in propagation of the polarization
from one cell to another. Thus, a QCA wire can be formed by arranging the
QCA cells in a series in which all the neighboring cells will get the polarization
of the driver cell (input). The binary wire is shown in Fig. 4 (a). Two wires in
QCA can cross without interaction. This is because QCA provides an inverter
chain of QCA cells, in which the dots in each cell are rotated by 45 ⓦ (This is
not the same as in QCA inverter). Each cell in this arrangement has opposite
polarization of their neighbors as they interact inversely. The inverter chain is
showninFig. 4 (b). In QCA, when a binary wire crosses the inverter chain, there
is no interaction between the two; hence the signals in the inverter chain and
binary wire can pass over each other. In QCA computing, the clock helps in
the synchronization of circuits and provides the power required for functionality.
QCA clocking consists of four phases: switch, hold, release and relax, as shown
in Fig. 5 [ 25 , 34 ]. During the switch phase, the barriers are raised and the cells
become polarized, depending on the state of its adjacent cell. The states of
the cells are fixed during this stage. During the hold phase, the barriers are
maintained at a high value. This helps the outputs to drive the inputs of the
next stage, which is in the switching phase. In the release phase, the barriers
are lowered and the cells are allowed to relax to an unpolarized state. During
the relaxed phase, the cells remain in an unpolarized neutral state. The cells in
QCA are connected to 4 clocking zones, each lagging behind by 90 ⓦ in phase.
QCA clocking helps in the successive transfer of information from one clock zone
to the next. Therefore, we have information flow from the input to the output
in a pipelined fashion [ 1 ].

2.3 Related Work

The research on reversible logic is expanding towards both design and synthe-
sis. In the synthesis of reversible logic circuits there has been several inter-
esting attempts in the literature such as in [ 22 , 40 , 51 , 59 , 75 ]. The researchers
have addressed the optimization of reversible logic circuits from the perspec-
tive of quantum cost and the number of garbage outputs. Recently, in [ 20 , 21 ]