Graphics Reference
In-Depth Information
Fig. 3.6
SOC ADAS heterogeneous architecture
The dual core A15's on TDA2x run at 750 MHz with an out-of-order superscalar
pipeline with a tightly coupled low-latency level-2 cache with additional improve-
ments in floating point and NEON
TM
. The dual core Cortex M4, is an efficient
controller engine for streaming image capture. TI's IVA-HD core is an imaging and
video codec accelerator that runs at 532 MHz to enable full HD video encode and
decode. Even with all of this compute power, vision analytics is still critically depen-
dent on the TMS320C66x DSP for high-level vision and Vision AcceleratorPAC
EVE for low- and mid-level vision to meet the challenging requirements.
The Vision AccelerationPac (EVE) is an accelerator purposely built for computer
vision, fully programmable in a high-level language environment, which delivers
more than eight times improvement in compute performance for advanced vision
analytics than existing ADAS systems at same power levels. The Vision Accel-
erationPac for this family of products includes multiple embedded vision engines
(EVEs) offloading the vision analytics functionality from the application processor
while also reducing the power footprint.
Today's SOC architectures enable further efficiencies by integrating all of the
peripherals necessary for a complete video/image processing system within a single
chip. Given the lack of interoperability specification for lidar, laser, radar, and video
data in the car network and that today the industry is using multiple data communi-
cation standards (i.e., camera, display, Ethernet AVB, LVDS, CAN, etc.) the SOC
must support a swarm of interfaces to ensure adoption across a broad spectrum of
possible use cases.
