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In-Depth Information
The sensor network community has developed several camera nodes. Rahimi
et al. [
23
] describe the Cyclops imager for wireless sensor networks. The image
sensor provides a maximum resolution of CIF quality (352
288). The camera
module can perform demosaicing, image scaling, color correction, tone correction,
and color space conversion. An 8-bit ATMEL ATmega128L processor controls the
camera. AXilixn CPLDoperates as a lightweight, low-power frame grabber. Cyclops
provides 64kB of SRAM and 512kB of flash. Chen et al. [
3
] designed the CITRIC
camera for low-bandwidth wireless sensor network applications. The device includes
a 1280
×
1024 pixel image sensor, a mono microphone with sample rates ranging
of 8-48 ks/s, an Intel XScale PXA270 processor with scalable clock frequencies,
64MB RAM and 16MB ROM; it is designed to connect to the TelosB sensor node
board with dimensions of about 2
×
×
2
. They measured the power consumption of
CITRIC running a background substraction algorithm at 970mW at a clock speed
of 520MHz. They reported the execution time of several vision algorithms: 340ms
for a Canny edge detector using the Intel Integrated Performance (IPP) primitives;
140ms for a median filter not using IPP and 34ms for a median filter using IPP.
Several sensors have been developed with on-sensor image analysis. These analy-
sis circuits are generally analog functions that perform simple, relatively fixed oper-
ations at very low energy and high speed. Liu et al. [
16
] describe a CMOS image
sensor with on-chip motion detection. Their sensor operates in three modes. Event
generation mode identifies events by computing frame-to-frame luminance differ-
ences; a given number of pixels exceeding a difference threshold generates an event.
Motion tracking mode uses 1-D Gaussian filters to smooth the image to generate
row and column events. Video output mode provides full-resolution and compressed
image output of the region of interest. Dubois et al. [
6
] designed a 64
64 CMOS
image sensor that can perform high-speed gradient analysis. They designed an octag-
onal photodiode to reduce wire lengths to adjacent pixels. The area between sets of
four adjacent pixels is occupied by an analog multiplier that performs the function
V
1
cos
×
. They showed how to use the function
to implement the Sobel operator and Laplacian.
Several groups have also designed ultra low-power image sensors. These sensors
generally offer lower resolution but at extremely lowenergy levels. Energy harvesting
has been successfully applied to a variety of ultra low-power systems and some recent
work has explored energy harvesting for image sensors. Hanson and Sylvester [
12
]
describe an ultra-low power sensor. Their test chip provides 128
(β)
+
V
2
sin
(β)
−
V
3
sin
(β)
−
V
4
sin
(β)
128 pixels and
is designed to operate over a range of power supply voltages from 0.45 to 0.7 V. It
consumes 140nJ per frame at 8.5 frames/s. Tang et al. [
8
] describe a CMOS image
sensor with an energy harvesting mode. The imager has two modes, one for imaging
and the other for harvesting energy from light using the pixels. In energy harvesting
mode, the sensor can harvest 80nA at 350 lux and 9.7
×
µ
A at 3,500 lux. Their sensor
has a resolution of 128
W at 10 frames/s. At these
rates of energy harvesting and usage during imaging, the energy required to capture
one frame can be provided through 200ms of energy harvesting.
×
96 pixels and consumes 10
µ
