Graphics Reference
In-Depth Information
by detecting unreliable disparity candidates analyzing their local distribution. The
design also mapped into the FPGA also includes the internal FIFO and all the other
modules depicted in Fig.
5.2
.
For evaluation purposes, we provide in Fig.
5.1
experimental results concerned
with the three implemented algorithms processing frame
66 of the KITTI dataset
[
10
]. Observing the figure, where in the disparity maps brighter greyscale levels
encode closer points and darker levels farther points, we can see that all three algo-
rithms enable us to obtain dense and fairly accurate disparitymaps of this challenging
stereo pair. Observing the trees in the right side of the reference frame, we can notice
that the SGM algorithms seems less noisy compared to the two local algorithms. In
the same figure, we can also notice the most unreliable (e.g., occlusions) and uniform
regions (e.g., shadows) are correctly detected by the postfiltering modules.
At this link
http://www.youtube.com/watch?v=KXFWIvrcAYo
is available a
video
2
concerned with an outdoor sequence processed by our modified version of the
SGM algorithm implemented on the outlined constrained target architecture. In this
case, the stereo camera, based on a Spartan 6 Model 75, was configured with a very
short baseline of about 4 cm. Observing this video, we can notice that the camera
provides, at high frame rate, very accurate and dense depth maps processing stereo
pairs at 640
480 resolution. In the video, we can also notice that the outlier detec-
tion module implemented into the FPGA correctly detects most unreliable disparity
measurements.
×
5.7 Conclusions
In this chapter, we have reviewed stereo vision algorithms that, with appropriate
modifications, are suited for implementation on a basic computing architecture made
of a single low-cost FPGA without additional external devices. Algorithms mapped
on such architecture provide accurate and dense depth maps in real time enabling to
obtain a small, low-power, and low-cost RGBD stereo vision sensor self-contained
into an FPGA.
Acknowledgments
I'd like to thank Ilario Marchio, Marco Casadio, Stefano Bruciati, Michael
Cavina, Simone Calisesi and Marco Destro for the experimental results reported in this paper.
References
1. Aysu A, Sayinta M, Cigla C (2013) Low cost FPGA design and implementation of a stereo
matching system for 3D-TV applications. In: VLSI-SoC, pp 204-209
2. Bailey DG (2011) Design for embedded image processing on FPGAs. Wiley, Asia
2
Other videos available at:
