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Fig. 5.9 Incremental techniques, referred to as box-filtering, aimed at reducing to a constant value
the number of basic operations required for cost aggregation in fixedwindow. To p , full cost computa-
tion. Middle , incremental optimization along horizontal direction (number of elementary operations
reduced by a factor N ). Bottom , vertical optimization required to compute the sum of the vertical
stripes shown in the middle of the figure. In this latter case, the full cost for each disparity value, is
computed with a fixed number of operations involving the four points highlighted at the bottom of
the figure in reference and target images
In deploying this 1D optimization strategy, the number of operations is reduced by a
factor N, manageable with the logic included in most FPGAs. Nevertheless, a further
reduction of operations can be obtained by deploying a 2D incremental scheme that
stores intermediate results for each column as depicted in the bottom of the figure.
In this case, the number of operations per window is constant and independent of the
size of the support, though compared to the brute force approach depicted at the top
of the figure, at the expense of a higher memory footprint for buffering intermediate
results required to sustain the additional 2D incremental calculation.
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