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In-Depth Information
Fig. 5.8
Multiple filters applied to the reference and target images for cost aggregation. The number
of filter is equal to the disparity range (
d
max
+
1 in the figure)
According to Fig.
5.7
, in this case filtering consists in summing/averaging within
the support, for each disparity value, the matching costs in the DSI. From a different
point of view, this operation consists in applying multiple instances of the same
filter (sum/average filter for FW) between reference and target image as illustrated
in Fig.
5.8
.
With a support of size
M
, the number
of arithmetic operations for the brute force approach is proportional to
M
×
N
and a disparity range of
[
0
,
d
max
]
×
N
×
(
d
max
+
=
1). Considering that plausible values for these parameters could be
M
=
=
15,
N
63, the number of arithmetic operations required might
exceed the hardware resources available in the target FPGA. Nevertheless, this num-
ber of operations can be significantly reduced by adopting well-known incremental
calculation schemes such as
box-filtering
[
21
]or
integral images
[
40
]. The former
in particular, as outlined in Fig.
5.9
, is particularly suited for FPGA implementation
of the FW algorithm.
The figure shows that the overall cost aggregation for the supports depicted in
the upper side of the figure can be obtained more efficiently by deploying the 1D
optimization depicted in the middle of the same figure. In fact, the aggregate costs
required by the operations in the upper side of Fig.
5.9
can be reduced by observing
that the overall cost for the central point can be obtained by updating the overall cost
computed in the previous position along the scanline, adding the aggregated costs of
the rightmost columns, and subtracting the aggregated costs of the leftmost columns.
15, and
d
max
