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Standard formal neuron, which is a combination of the input adder, the nonlinear
transducer, and the branch point at the output
On the basis of these elements neural chips are produced from which the
required neural network can be assembled.
Nowadays industry of various countries produces dozens of digital, analog, and
hybrid neural chips, including neural chips with a rigid neuron structure (hard-
wired) and neural chips with a custom structure (reprogrammable). Typically 32-
256 neurons with the word length of variables 16-8 bits are formed on the chips.
They are manufactured based on silicon planar semiconductor technology.
As an example, let us consider neural chips with programmable weight coeffi-
cients developed by Bell Laboratories in 1987.
In order to allow adjustment of weight coefficients of the neural network, a
specialized circuit employing a combined technology was designed such that both
the neural network and the memory for controlling reprogramming of weight
coefficients were placed on a single chip. Digital input and output signals are
used by the circuit. To calculate the output of the neural network analog circuits
for multiplication and summation were used, while digital signals served to control
the functioning of the circuit.
This VLSI was manufactured using the 2.5
μ
m CMOS technology and contained
approximately 75,000 transistors. The 6.7
7 mm crystal accommodated 54 oper-
ating amplifiers performing the functions of neurons and 5 kilobytes of static RAM
for reprogramming weight coefficients on the crystal. The circuit allowed to
implement a neural network with full connectivity. The 54
54 matrix of connec-
tion coefficients occupied about 90 % of the crystal surface and allowed for
connecting the output of any neuron to the input of any other neuron.
4.4 The Future of Neurocomputing: The Dubious Legacy
of Digital Computers
The
intense
revival of neural
representations
and the development of
neurocomputers became a reality in recent years.
Nevertheless, despite the fact that the neural network paradigm is rooted in the
1940s of the last century, approaches to its optimal practical implementation in
hardware were hardly considered for many years. Therefore, the establishment of
neurocomputers took a conventional path—the use of semiconductor circuitry and
planar technology, well proven in a variety of microelectronic devices.
It must be admitted that so far, in fact, there is no alternative to semiconductor
circuitry and the technology being used to simulate neurons and neural networks.
This is easily explained because, due to enormous advantages of the planar tech-
nology, it all but outcompeted almost all previously proposed technological
implementations of computing devices. Moreover, discrete circuitry was created
to implement the von Neumann architecture. In this sense, the von Neumann
