Hardware Implementation of Embedded Fuzzy Controllers on FPGAs and ASICs - Fuzzy Modeling and Control: Theory and Applications - page 230

This condition is always fulfilled for systems using the product operator as antecedent
connective and triangular membership functions with an overlapping degree equal
to two.
Memory-based MFCs obtain the antecedent activation levels in only one clock
cycle, whereas arithmetic MFCs need as many clock cycles to perform its opera-
tion as membership functions are defined. At the inference stage, a clock cycle is
required by the active-rule selection mechanism to evaluate each active rule. Finally,
for systems requiring division at the output stage, a sequential circuit based in non-
restoring techniques needs a clock cycle for each bit of the quotient. Using pipeline
techniques, the number of required clock cycles to produce an inference is limited by
the maximum between the number of active rules and the number of cycles required
to perform the operations of the fuzzifier and defuzzifier interfaces.

13.3 Synthesis of Fuzzy Controllers with xfsg

FPGAmanufactures have recently developed different design tools to ease the imple-
mentation of digital signal processing (DSP) algorithms on programmable devices.
An example of this kind of products is the System Generator tool (XSG) offered by
Xilinx, which is integrated into the /Simulink environment, thus allowing

the application of a model-based design flow on Xilinx's devices. XSG provides
basic building blocks for digital systems design gathered into a Simulink library
called “Xilinx Blockset”, as well as the software required to translate Simulink mod-
els using these blocks to HDL descriptions that can be implemented on FPGAs
(SysGen 2010 ).
One of the design techniques provided by Xfuzzy 's hardware synthesis tools is
based on XSG. To give support to this design strategy the library XfuzzyLib has

Matlab

Fig. 13.3 Components of XfuzzyLib grouped by functionalities: control elements, MFCs, active
rule selectors, antecedent connectives, rule memories, defuzzifiers, division, archetypal fuzzy logic
controllers (FLCs), and crisp blocks