VLSI Models of Computation - Models of Computation: Exploring the Power of Computing - page 577

Geometric design rules specify the amounts of overlap of and separation between metal and
dopant rectangles that are needed to guarantee the desired electrical and electronic properties of
a VLSI circuit. If wires are too thin, electrons, which move through them at very high speeds,
can cause excess heating as well as dislodge atoms and create an open circuit (this is called
metal migration ), especially at points at which a wire bends to descend into a well created
during chip fabrication. Similarly, if wires are too close, an error in registration of masks may
cause short circuits between wires. Also, since transistors are constructed through the doping
and overlaying of insulating and conducting materials, if the regions defining a transistor are
too small, it will not behave as expected.
The geometric design rules for a particular chip technology can be quite complex. For the
purpose of analysis they are simplified into a few rules concerning the width and separation
of rectangles, the amount of area required for contacts between wires on layers separated by
insulation, and the size of the various rectangular regions that form gates and transistors. As
suggested by this discussion, a VLSI chip is quasiplanar ; that is, its components lie on a few
layers, which are separated by insulation except where contacts are made between layers.
12.1.2 Design and Layout
Many tools and techniques have been developed to address the complexity of chip layout.
Typically these tools and techniques use abstraction; that is, they decompose a problem into
successively lower level units of increasing complexity. At each level the number of units in-
volved in a design is kept small so that the design is comprehensible.
The design of a VLSI chip begins with the specification of its functionality at the func-
tional or algorithmic level . Either a function or an algorithm is given as the starting point.
An algorithm is then produced and translated into a specification at the architectural level .
At this level a chip is specified in terms of large units such as a CPU, random-access memory,
bus, floating-point unit, and I/O devices. (The material of Chapters 3 and 4 is relevant at this
level.) After an architectural specification is produced, design commences at the logical level .
Here particular methods for realizing architectural units are chosen. For example, an adder
could be realized either as a ripple or a carry-lookahead adder depending on the stated speed
and cost objectives. (The material of Chapter 2 applies at this level.)
At the gate level , the next level in the design process, a technology, such as NMOS and
CMOS, is chosen in which to realize the transistors and wires. This involves specifications of
widths for wires, the number of layers of metal, and other things. If new transistor layouts are
used, their physics is often simulated to determine their electrical properties.
At the next level, the layout level , a gate-level design is translated into physical positions for
modules, gates, and wires. Often at this level a rough layout is produced manually, after which
automatic routing and compaction algorithms are invoked to route wires between modules
and squeeze out the unnecessary area. Space must be reserved on each layout for I/O pads ,
rectangular regions large enough to connect external wires. They serve as ports through which
data is read and written. Because these wires and pads are very large by comparison with the
wires on the chip, there is a practical limit on the number of I/O ports on a chip. A port can
be both an input and an output port.
Once a layout is complete it is usually simulated logically, that is, at the level of Boolean
gates. Parts of it may also be simulated electrically, a much more time-consuming process given
the much lower level of detail that it entails.