Machines with Memory - Models of Computation: Exploring the Power of Computing - page 144

the opcode register OPC and 0 otherwise. These instruction variables can be generated by a
decoder attached to the output of OPC. Here

¬

A denotes the complement of the accumulator.
Now that we understand how to combine microinstructions in microcycles to produce
macroinstructions, we use this information to define control variables that control the move-
ment of data between registers or combine the contents of two registers and assign the result
to another register. This information will be used to complete the design of the CPU.
We now introduce notation for control variables . If a microinstruction results in the
movement of data from register B to register A , denoted A

B in our assignment nota-
tion, we associate the control variable L ( A , B ) with it. If a microinstruction results in the
combination of the contents of registers B and C with the operation

←

and the assignment

of the result to register A , denoted A

← B C in our assignment notation, we associate

the control variable L ( A , B

C ) with it. For example, inspection of Figs. 3.36 and 3.37
shows that we can write the following expressions for the control variables L ( OPC, MDR )
and L ( AC, AC + MDR ) :

L ( OPC, MDR )= t 3
L ( AC, AC + MDR )= c ADD ∧ t 6

Thus, OPC is loaded with the contents of MDR when t 3 = 1, and the contents of AC are
added to those of MDR and copied into AC when c ADD ∧

t 6 = 1.
The complete set of control variables can be obtained by first grouping together all the mi-
croinstructions that affect a given register, as shown in Fig. 3.38 , and then writing expressions
for the control variables. Here M denotes the memory unit and HLT is a special register that
must be set to 1 for the CPU to run. Inspection of Fig. 3.38 leads to the following expressions
for control variables:

L ( AC, AC + MDR )= c ADD ∧ t 6

L ( AC, AC AND MDR )= c AND ∧ t 6

L ( AC, 0 )= c CLA ∧ t 4

L ( AC, Shift(AC) )= c CIL ∧ t 4

L ( AC, MDR )= c LDA ∧ t 6

L ( AC, INR )= c IN ∧ t 4

L ( AC, ¬

AC )= c CMA ∧

t 4

L ( MAR, PC )= t 1
L ( MAR, MDR )=( c ADD ∨ c AND ∨ c LDA ∨ c STA ) ∧ t 4

L ( MDR, M )= t 2 ∨ ( c ADD ∨ c AND ∨ c LDA ) ∧ t 5

L ( MDR, AC )= c STA ∧ t 4

L ( M, MDR )= c STA ∧ t 5

L ( PC, PC + 1 )= t 2
L ( PC, MDR )=( AC = 0 ) ∧ c JZ ∧ t 4

L ( OPC, MDR )= t 3
L ( OUTR, AC )= c OUT ∧ t 4

L ( t j )= c HLT ∧ t 4 for 1 ≤ j ≤ 6