Information Technology Reference
In-Depth Information
Timing Microinstructions
t
1
←
MAR
PC
t
2
←
←
PC
+
1
MDR
M, PC
t
3
←
OPC
MDR
Figure 3.36
The microcode for the fetch portion of each instruction.
sive microcycles. The
j
th
microcycle is specified by the
timing variable
t
j
,1
k
.That
is,
t
j
is 1 during the
j
th
microcycle and is zero otherwise. It is straightforward to show that
these timing variables can be realized by connecting a decoder to the outputs of a counting
circuit, a circuit containing the binary representation of an integer that increments the integer
modulo some other integer on each clock cycle. (See Problem
3.40
.)
Since the fetch portion of each instruction is the same, we write a few lines of register
transfer notation for it, as shown in Fig.
3.36
. On the left-hand side of each line is timing
variable indicating the cycle during which the microinstruction is executed.
The microinstructions for the execute portion of each instruction of our computer are
shown in Fig.
3.37
. On the left-hand side of each line is a timing variable that must be
AND
ed
with the indicated
instruction variable
,suchas
c
ADD
, which is 1 if that instruction is in
≤
j
≤
Control
Microcode
Control
Microcode
ADD
c
ADD
STA
c
STA
t
4
MAR
←
t
4
MAR
←
MDR
MDR
c
ADD
t
5
MDR
←
c
STA
t
4
MDR
←
M
AC
c
ADD
t
6
←
AC
+
MDR
c
STA
t
5
M
←
AC
MDR
AND
c
AND
CMA
c
CMA
t
4
MAR
←
t
4
←¬
MDR
AC
AC
c
AND
t
5
MDR
←
M
c
AND
t
6
←
AC
AC
AND
MDR
JZ
c
JZ
t
4
if ( AC
=
0) PC
←
MDR
CLA
c
CLA
t
4
AC
←
0
IN
c
IN
t
4
AC
←
INR
CIL
c
CIL
t
4
AC
←
Shift(AC)
OUT
c
OUT
t
4
OUTR
←
AC
LDA
c
LDA
t
4
MAR
←
MDR
HLT
c
HLT
c
LDA
t
5
MDR
←
M
t
4
t
j
←
≤
j
≤
k
0for1
c
LDA
t
6
←
AC
MDR
Figure 3.37
The execute portions of the microcode of instructions.
Search WWH ::
Custom Search