Machines with Memory - Models of Computation: Exploring the Power of Computing - page 139

3.10.2 The Fetch-and-Execute Cycle
The fetch-and-execute cycle has a fetch portion and an execution portion. The fetch portion
is always the same: the instruction whose address is in the PC is fetched into the MDR and
the opcode portion of this register is copied into the OPC. At this point the action of the CPU
diverges, based on the instruction denoted by the value of the OPC. Suppose, for example,
that the OPC denotes a load accumulator instruction. The action required is to copy the word
specified by the address part of the instruction into the accumulator. Fig. 3.32 contains a de-
composition of the load accumulator instruction into eight microinstructions executed in six
microcycles . During each microcycle several microinstructions can be executed concurrently,
as shown in the table for the second and fourth microcycles. In Section 3.10.5 we describe
implementations of the fetch-and-execute cycle for each of the instructions of our computer.
It is important to note that a realistic CPU must do more than fetch and execute instruc-
tions: it must be interruptable by a user or an external device that demands its attention. After
fetching and executing an instruction, a CPU typically examines a small set of flip-flops to see
if it must break away from the program it is currently executing to handle an interrupt ,an
action equivalent to fetching an instruction associated with the interrupt. This action causes
an interrupt routine to be run that responds to the problem associated with the interrupt, after
which the CPU returns to the program it was executing when it was interrupted. It can do
this by saving the address of the next instruction of this program (the value of the PC) at a
special location in memory (such as address 0). After handling the interrupt, it branches to
this address by reloading PC with the old value.

3.10.3 The Instruction Set
Figure 3.33 lists the eleven instructions of our simple CPU. The first group consists of arith-
metic (see Section 2.7 ), logic, and shift instructions (see Section 2.5.1 ). The circulate in-
struction executes a cyclic shift of the accumulator by one place. The second group consists
of instructions to move data between the accumulator and memory. The third set contains
a conditional jump instruction: when the accumulator is zero, it causes the CPU to resume
fetching instructions at a new address, the address in the memory data register. This address
is moved to the program counter before fetching the next instruction. The fourth set contains
input/output instructions. The fifth set contains the halt instruction. Many more instruc-

Cycle Microinstruction Microinstruction

1 Copy contents of PC to MAR.

2 Fetch word at address MAR into MDR. Increment PC.

3 Copy opcode part of MDR to OPC.

4 Interpret OPC Copy address part of MDR

to MAR.

5 Fetch word at address MAR into MDR.
6 y Ri to .

Figure 3.32 Decomposition of the load accumulator instruction into eight microinstructions
in six microcycles.