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can be translated to a RASP program by replacing the names of RAM registers by the names
of random-access memory locations not used for storing the RAM program. The execution
of a RASP program directly parallels that of the RAM program; that is, the RASP alternates
between reading instructions and executing them. Since we do not consider the distinction
between RASP and RAM significant, we call them both the RAM.
3.5
Random-Access Memory Design
In this section we model the random-access memory described in Section
3.4
as an FSM
M
RMEM
(
μ
,
b
)
that has
m
=
2
μ
b
-bit data words,
w
0
,
w
1
,
...
,
w
m−
1
,aswellasaninput
data word
d
(
in wrd
), an input address
a
(
addr
), and an output data word
z
(
out wrd
). (See
Fig.
3.20
.) The state of this FSM is the concatenation of the contents of the data, input and
output words, input address, and the command word. We construct an efficient logic circuit
for its next-state and transition function.
To simplify the design of the FSM
M
RMEM
we use the following encodings of the three
input commands:
Name
s
1
s
0
no-op
00
read
01
write
10
An input to
M
RMEM
is a binary
(
μ
+
b
+
2
)
-bit binary tuple, two bits to represent a
command,
μ
bits to specify an address, and
b
bits to specify a data word. The output function
of
M
RMEM
,
λ
RMEM
, is a simple projection operator and is realized by a circuit without any
gates. Applied to the state vector, it produces the output word.
We now describe a circuit for
δ
RMEM
, the next-state function of
M
RMEM
. Memory words
remain unchanged if either
no-op
or
read
commands are executed. In these cases the value
of the command bit
s
1
is 0. One memory word changes if
s
1
=
1, namely, the one whose
b
w
m−
1
w
m−
1
cmd
out wrd
in wrd
w
m−
1
w
m−
1
addr
Figure 3.20
A random-access memory unit
M
RMEM
that holds
mb
-bit words. Its inputs
consist of a command (
cmd
), an input word (
in wrd
), and an address (
addr
). It has one output
word (
out wrd
).
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