Digital Signal Processing Reference
In-Depth Information
Input Signal,
x
(
k
)
Sampler &
ADC
x
(
t
)
DF
N
−bits
y
(
k
)
DCO
Output Pulses,
v
o
(
k
)
Fig. D.19
Block diagram of the SDPLL
between successive phase errors is smaller than some positive number (e.g., 0.01).
Also find the effect of the initial phase error on the locking speed assuming the
frequency ratio and the loop gain are fixed.
Task 2: Noise Analysis
Consider a sinusoidal input signal corrupted by an AWGN noise. Find the pdf
of the SDPLL output frequency for different SNRs. Discuss whether the SDPLL
can estimate the input frequency in noisy environments. Take several
combinations of the loop gain and the frequency ratio. Plot the variance of the
loop frequency estimate as a function of SNR.
B: Demodulation of PM Signals Using SDPLL
The first-order SDPLL can demodulate PM signals as shown in Fig.
D.20
below. Using MATLAB, simulate the PM demodulation circuit and study its
behavior under noise-free conditio ns for different values of the modulation index.
C: Second-Order SDPLL
The second-order SDPLL utilizes a proportional-plus-accumulation filter and
locks on zero phase. Simulate this loop and study its performance (as a frequency
estimator) in Gaussian noise. Note that two initial phases should be considered.
^
s
o
(
t
)
^
θ
k
≈
θ
(
t
)
Input PM Signal,
(
k
)
≈
Σ
i=0
x
(
i
)
x
(
k
)
Sampler &
ADC
DAC &
LPF
x
(
t
)
N
−bits
G
1
x
(
t
) = A sin[
ω
o
t
+
θ
(
t
)]
z
−1
[
θ
(
t
) =
α
m
(
t
) ]
DCO
v
o
(
k
)
Fig. D.20
Circuit diagram for PM demodulation using 1st-order SDPLL
