Selected Topics in Applied Signal Processing - Digital Signal Processing: An Introduction with MATLAB and Applications - page 146

Fig. 3.12 A block diagram
of a generic sinusoidal digital
phase-locked loop

Input Signal,

x ( k )

Sampler &
ADC

x ( t ) DF

N −bits

y ( k )

DCO

Output Pulses, v o ( k )

There are many kinds of DPLLs. The interested reader is referred to [ 4 , 5 ] for
more details.

3.4.2.1 The Sinusoidal DPLL (SDPLL)

Among DPLLs, non-uniform sampling sinusoidal PLLs are particularly popular.
Thy are simple to implement and suitable for relatively wide locking ranges. Fig-
ure 3.12 shows a block diagram of a generic SDPLL. It consists of a sampler/ADC
unit which serves effectively as a PED, a digital low-pass filter (DF), and a digital
voice-controlled oscillator (DCO) which produces a constant amplitude (but variable
frequency) output pulses that control the sampling instants of the Sampler/ADC unit.
Different SDPLLs can be obtained by having different D-LPFs. First and
second-order filters are both commonly used in practice for SDPLLs. The first-
order SDPLL uses a digital filter of zero-order, i.e., it consists of just a multipli-
cative constant G 1 . A second-order 00 typically uses a digital filter with the
following transfer function (see also Fig. 3.13 ):

1
1 z 1 :

H ð z Þ¼ G 1 þ G 2

where G 1 and G 2 are appropriately chosen constants. This transfer function can be
implemented in parallel form as shown in Fig. 3.13 . The output of this filter is
given by:

y ð k Þ¼ G 1 x ð k Þþ G 2 X

k

x ð i Þ

i ¼ 0

Fig. 3.13 The digital filter of
the 2nd-order SDPLL

G 1

G 2

x ( k ) y ( k )

z −1