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Selecting the appropriate partitioning scheme in accordance with the paralleliza-
tion model is of utmost importance to yield good speedups.
Implementing the Loop Partitioning in a shared memory platform was a
painful task due to the number of variables and its declaration 19 .Furthermore,
the debugging process was also very dicult. For these reasons, the per core
allocated workload on a shared memory model should be a simple task. Despite
the Loop Partitioning got higher performance than Loop/Task Partitioning, the
latter has several advantages such as: it is controllable; easy to implement; lower
implementation time and an easier debugging process.
Further work may explore using Intel's Threading Building Blocks (TBB) 20
to exploit dynamic load balancing among cores. On the other hand, to minimize
contentions regarding hard disk access, it can be worthwhile to use a dedicated
thread for that purpose.
References
1. Chen, G., Church, D., Englert, B., Henkel, C., Rohwedder, B., Scully, M., Zubairy,
M.: Quantum Computing Devices: Principles, Designs, and Analysis. Chapman &
Hall/CRC, New York (2006)
2. Hill, S., Wootters, W.K.: Entanglement of a Pair of Quantum Bits,
http://arxiv.org/abs/quant-ph/9703041
3. Pretel, A., Reina, J.H., Aguirre-Contreras, W.: Excitonic dynamics of a quantum dot
coupled to a laser-driven semiconductor microcavity. Microelectronics Journal 39,
682-684 (2008)
4. Altintas, F., Eryigit, R.: Quantum Correlations in non-Markovian Environments.
Physics Letters A 374, 4283-4296 (2010)
5. Intel Corp.: Optimizing Software for Multi-core Processors. White paper (2007)
6. Intel Corp.: Auto-parallelization overview. White paper (2007)
7. Valgrind Developers: Valgrind for dynamic analysis tools, http://valgrind.org/
8. Intel Corp.: Vtune performance profiler,
https://software.intel.com/en-us/intel-vtune-amplifier-xe
9. Bellomo, B., Lo Franco, R., Compagno, G.: Entanglement dynamics of two indepen-
dent qubits in environments with and without memory. Phys. Rev. A 77, 032342-
032351 (2008)
19 OpenMP requires the user to define which variables should be private to each core.
20 See: https://software.intel.com/en-us/intel-tbb
 
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