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Flexicache: Highly Reliable and Low Power
Cache under Supply Voltage Scaling
Gulay Yalcin
1
,
2
, Azam Seyedi
1
,
2
, Osman S. Unsal
1
, and Adrian Cristal
1
,
3
1
Barcelona Supercomputing Center
2
Universitat Politecnica de Catalunya
3
IIIA - Artificial Intelligence Research Institute - Spanish National Research Council
{
gyalcin,aseyedi,ounsal,acristal
}
@bsc.es
Abstract.
Processors supporting a wide range of supply voltages are
necessary to achieve high performance in nominal supply voltage and
to reduce the power consumption in low supply voltage. However, when
the supply voltage is lowered below the safe margin (especially close to
the threshold voltage level), the memory cell failure rate increases dras-
tically. Thus, it is essential to provide reliability solutions for memory
structures. This paper proposes a novel, reliable L1 cache design, Flexi-
cache, which automatically configures itself for different supply voltages
in order to tolerate different fault rates. Flexicache is a circuit-driven
solution achieving in-cache replication with no increase in the access la-
tency and with a minimum increase in the energy consumption. It defines
three operating modes: Single Version Mode, Double Version Mode and
Triple Version Mode. Compared to the best previous proposal, Flexi-
cache can provide 34% higher energy reduction for L1 caches with 2
×
higher error correction capability in the low-voltage mode.
1 Introduction
As energy is a key design concern for computer systems, microprocessors started
to provide 1) high-performance and 2) low-power operating modes [20]. Proces-
sors run at a high frequency by using the nominal supply voltage (
V
dd
)inthe
high-performance mode, and they reduce
V
dd
in the low-power mode to reduce
the energy consumption by trading-off performance. However, this energy reduc-
tion comes with a drastic increase in the number of failures especially in memory
structures (i.e on-chip SRAM memories such as L1 and L2 caches) [11,15]. These
memory failures can be persistent (i.e. yield loss or hard errors) or non-persistent
(i.e. soft errors or erratic bits) while rates of both failures increase as the
V
dd
is
decreased. Moreover transistor scaling increases the vulnerability of transistors
to radiation events since it increases the likelihood of having multibit soft errors
on adjacent bits [7]. Thus, it is essential to implement reliability solutions ad-
dressing both persistent and non-persistent failures in caches in order to reduce
the
V
dd
and provide reliable cache operation for future technology nodes. There
are two main techniques to deal with high fault rates stemming from the above
issues: 1) Coding techniques such as parity or ECC, 2) In-cache replication.
While they are effective, both mechanisms have issues.
