Information Technology Reference
In-Depth Information
Table 3-7: The CSW contains status and related information about a command.
Name
Bits
Description
dCSWSignature
32
The value 53425355h, which identifies the structure as a
CSW. The LSB (55h) transmits first on the bus.
dCSWTag
32
The value of the dCBWTag in a CBW received from the
host.
dCSWDataResidue
32
For transfers where the host sends data to the device in
the data-transport phase, the difference between
dCBWDataTransferLength and the number of bytes the
device processed.
For transfers where the device sends data to the host in
the data-transport phase, the difference between
dCBWDataTransferLength and the number of valid
bytes the device has sent, excluding any pad bytes.
bCSWStatus
8
00h = command passed.
01h = command failed.
02h = phase error. Host should perform a reset recovery.
In a command where the device sends data in the data-transport phase,
dCSWDataResidue contains the difference between dCBWDataTransfer-
Length in the command's CBW and the amount of valid data the device
sent, excluding any pad bytes. If the device has sent dCBWDataTransfer-
Length bytes, dCSWDataResidue is zero.
The bCSWStatus field indicates whether the command completed without
error. A value of 00h means success. A value of 01h means the command
failed and the host should immediately issue a SCSI REQUEST SENSE
command to get status information. The protocol that causes the host to
send REQUEST SENSE on receiving a response code of 01h is sometimes
called auto sense because the host's USB driver, rather than higher-level
code, requests the status information. The handling of the error and sense
data is thus “automatic” to higher-level software. Chapter 6 has more about
the REQUEST SENSE command.
A value of 02h means that the host should perform a reset recovery on the
device. A reset recovery consists of the following control transfers in order:
1. Bulk-only Mass Storage Reset. On completion of the request, the
device is ready to receive a new CBW. The reset should not change the
states of data-toggle bits and endpoint STALL conditions. This is a
 
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