MultiMediaCard Protocol - USB Mass Storage: Designing and Programming Devices and Embedded Hosts - page 104

is that the card delays just zero to eight cycles between the response token
and the register data.
In a write operation, after sending a command and receiving a response, the
host generates at least 8 clock cycles before sending a data token (NWR).
There is no maximum number of clock cycles before the data token. The
card's response follows the data token immediately. The host then waits for
the DataOut line to return high to indicate that the card has programmed
Figure 5-1: Timing for block-read and block-write commands.