Accessing Flash Memory Cards - USB Mass Storage: Designing and Programming Devices and Embedded Hosts - page 87

chronous serial port used by serial EEPROMs and other peripheral chips.)
When using SPI, the port can function as a host or device. Table 4-4 shows
the port pins used by the chip's SPI port.
Registers
The PIC18F4550 has six registers that store information related to SPI com-
munications.
The MSSP Status Register (SSPSTAT) contains status and control infor-
mation relating to the port. Table 4-5 shows the functions of the SSPSTAT
bits.
MSSP Control Register 1 (SSPCON1) contains additional status and con-
trol information relating to the port. Table 4-6 shows the functions of the
SSPCON1 bits.
The Serial Receive/Transmit Buffer Register (SSPBUF) holds a received
byte or a byte waiting to transmit.
The MSSP Shift Register (SSPSR) holds the bits in a byte being received
or a byte that is transmitting. Firmware can't access the SSPSR.
In Peripheral Interrupt Enable Register 1 (PIE1), bit 3 is the master SPI
interrupt enable bit. When the bit equals 1, the interrupt is enabled.
In Peripheral Interrupt Request (Flag) Register 1 (PIR1), bit 3 is the mas-
ter SPI interrupt flag bit. When this bit equals zero, the SPI port is waiting
to transmit or receive. When the bit equals 1, a transmit or receive opera-
tion is complete. Firmware that uses this interrupt should clear the bit in
the interrupt-service routine that services the interrupt.
Microchip's MPLAB C18 C compiler provides a processor definition mod-
ule for the PIC18F4550 (p18f4550.asm). The module defines names for the
registers. These declarations from the compiler file p18F4550.h enable
accessing SSPBUF and the bits in SSPCON1 and SSPSTAT:
extern volatile near unsigned char SSPBUF;
extern volatile near unsigned char SSPCON1;
extern volatile near unsigned char SSPSTAT;