Accessing Flash Memory Cards - USB Mass Storage: Designing and Programming Devices and Embedded Hosts - page 83

If the PIC18F4550 or another MultiMediaCard host is powered at 3.3V, the
level-translation circuits are unneeded and the host can interface directly to
the MultiMediaCard, but the maximum clock frequency (at Fosc) is 16
Mhz.
Host Programming
To communicate with a MultiMediaCard, the host uses the MultiMedi-
aCard protocol to send commands, receive responses, and send and receive
additional data as required by commands. On a lower level, the commands,
responses, and data each consist of one or more bytes. This chapter explains
how the individual bytes travel on the SPI bus. Chapter 5 describes the pro-
tocol for sending MultiMediaCard commands.
Configuring
SPI is a synchronous bus, where the host provides a clock signal that deter-
mines when the host and MultiMediaCard read and write data. The inter-
face provides options for configuring the clock polarity and the phase, or
timing, relationship between the clock and data bits. The clock polarity
determines whether the clock is high or low when idle. The clock phase
determines whether input data is valid on the rising or falling clock edge.
For MultimediaCards, the clock line must be high when idle and data is
valid on the rising clock edge.
SPI hosts are generally more flexible than SPI devices. Microcontrollers with
SPI support typically provide configuration registers for selecting a clock
polarity and phase to match a device's requirements.
Figure 4-2 and Table 4-3 show the timing requirements for MultiMedi-
aCards. The cards latch data received on the DataIn line on SCLK's rising
edge. The data must be valid 3 nanoseconds before and after the rising edge.
When sending data on DataOut, the data is valid at least 5 nanoseconds
before and after SCLK's rising edge. In practice, MultiMediaCards typically
latch output data on SCLK's falling edge, so the data is valid for a longer
period.
Data on the bus travels most significant bit first. Transmitting a byte
requires eight clock cycles. The host must generate clock cycles when trans-