Summary and Conclusions - Hierarchical Neural Networks for Image Interpretation - page 216

similar to parallel computers, while keeping size and power consumption compati-
ble with desktop PCs. It is conceivable that such specialized chips could be used as
input processors in future PCs, similar to the dedicated graphic processors widely
employed today. An even greater degree or parallelism is possible when using bit-
serial computations or systolic arrays with thousands of processing elements.
Of course, designing special-purpose VLSI hardware to match the proposed ar-
chitecture offers the greatest possibilities for speed-up and reduction of size/power,
but involves significant development costs and time. Hence, this is only feasible for
high-volume mobile applications, e.g. for use in cars or in PDAs/cellular phones.
While field-programmable gate array (FPGA) chips can be used for prototyping,
custom design is necessary to take full advantage of cost and efficiency advantages.
Since the processing in the Neural Abstraction Pyramid is fully parallel, low operat-
ing frequencies can be used. This reduces the voltage needed, and hence the power
consumption.
At least one additional order of magnitude can be gained in efficiency by us-
ing analog, instead of digital, VLSI [124]. Analog chips use only a single value to
represent a quantity, instead of multiple bits. Furthermore, transistors do not switch,
but are kept below saturation. Operations that are costly in digital VLSI, such as
multiplications, can be implemented with few analog transistors. On the other hand,
the precision of these operations is limited, and analog VLSI is susceptible to noise
and substrate inhomogeneities. Analog VLSI offers the possibility of integrating
processing elements and photosensors on the same chip in order to avoid I/O bot-
tlenecks. One example for such a tight integration is the implementation of cellular
neural networks (CNN) on the focal plane [143].
Similar to LCD displays or CMOS cameras, defects of single processing ele-
ments can be tolerated if the resolution is high. This allows for producing large
chips containing millions of processing elements with high yields. Another excit-
ing possibility is the trend towards 3D integration. Connecting a stack of chips with
dense arrays of vias keeps wire length short and allows for the combination of chips
that need different production processes. One example of such vertical interconnects
is the SOLID process, recently announced by Infineon [3], that reduces the size of
vias to 10 µm × 10 µm . It offers the possibility of establishing a direct correspon-
dence between the layers of the Neural Abstraction Pyramid and the stack levels.
The tight integration of image sensors and massively parallel hierarchical process-
ing could yield inexpensive, small, low power devices that have the computational
power of today's supercomputers for computer-vision tasks. They will be needed to
allow mobile computers to perceive their environment.
11.3.2 Using more Complex Processing Elements
The simple processing elements, used in the Neural Abstraction Pyramid, resemble
feed-forward neural networks with a single output-unit. It would be interesting to
investigate the use of more complex processing elements. One possibility would be
to employ units that are biologically more realistic. They could generate spikes and