Introduction - Control of Power Inverters in Renewable Energy and Smart Grid Integration - page 39

2. it is supported with MATLAB R Embedded Coder (originally, Target Support Package)
and, hence, codes for real-time execution can be generated automatically from Simulink R

models, which saves a lot of time for development;
3. Texas Instruments run a worldwide university program 1 that provides excellent, and often
free, support to educators, researchers and students in all phases of course curricula, senior
design and research projects.

1.3.7.1 Overview of TI DSC TMS320F28335

Figure 1.37 shows the functional block diagram of TI DSC TMS320F28335 (TI 2007).
It includes the same 32-bit fixed-point architecture as TI's existing C28x DSCs, but also
include a single-precision (32-bit) IEEE 754 floating-point unit (FPU). It is a very effi-
cient C/C++ engine, enabling users to develop their system control software in a high-
level language. It also enables math algorithms to be developed using C/C++. The device
is as efficient at DSP math tasks as it is at system control tasks that typically are han-
dled by micro-controller devices. This efficiency removes the need for a second processor
in many systems. The 32 32-bit MAC 64-bit processing capabilities enable the controller to

handle high numerical resolution problems efficiently. Add to this the fast interrupt response
with automatic context save of critical registers, resulting in a device that is capable of servic-
ing many asynchronous events with minimal latency. The device has an 8-level-deep protected
pipeline with pipelined memory accesses. This pipelining enables it to execute at high speeds
without resorting to expensive high-speed memories. Special branch-look-ahead hardware
minimises the latency for conditional discontinuities. Special store conditional operations fur-
ther improve performance. TMS320F28335 comes with 256 K

×

× 16 Flash, 34 K × 16 SARAM

on-chip memory. There are two lower versions: F28334 with 128 K × 16 Flash, 34 K × 16

SARAM on-chip memory and F28332 with 64 K 16 SARAM on-chip

memory. The equivalent versions that do not include the FPU are F2823x.
The 2833x/2823x devices implement the standard IEEE 1149.1 JTAG interface. Addi-
tionally, the devices support real-time mode of operation whereby the contents of memory,
peripheral and register locations can be modified while the processor is running and executing
code and servicing interrupts. The user can also single step through non-time critical code while
enabling time-critical interrupts to be serviced without interference. The device implements
the real-time mode in hardware within the CPU. This is a feature unique to the 2833x device,
requiring no software monitor. Additionally, special analysis hardware is provided that sets
the hardware breakpoint or data/address watch-points and generates various user-selectable
break events when a match occurs.
The 2833x/2823x devices provide options to boot normally or to download new software
from an external connection or to select boot software that is programmed in the internal
Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for
use in math-related algorithms. The 2833x devices support high levels of security to protect
the user firmware from being reverse engineered.

× 16 Flash, 26 K ×

1 http://e2e.ti.com/group/universityprogram/default.aspx?DCMP=univ&HQS=university