Hardware Reference

In-Depth Information

3.1.1 Slow Dynamic Systems

If a continuous-time dynamic system is sampled such that the sampling rate

is fast in comparison to the desired bandwidth then the discretization induced

delay in the system can be considered negligible. Such a dynamic system is

referred to as slow dynamics system. A commonly used design method for

such system is as follows:

Step 1, Obtain, using identification or physical modeling, a suitable model

P(s) of the plant. Model the delay T
d
due to digital control as P
d
(s)=

e
−T
d
s
which can be expressed as
−
0.5T
d
s+1

0.5T
d
s+1

;

Step 2, Design a continuous-time controller C(s)forP(s)P
d
(s)usingoneof

the many well-known design methods, such as LQR, LQG/LTR, H
2
, H
∞
,

etc;

Step 3, Use transformation method such as the bilinear transformation

s =
2

T

z
−
1

z +1

(3.1)

to convert C(s) to digital controller C(z). Then the discrete-time con-

troller C(z) can be implemented using a µ-controller or DSP.

Conversion of continous-time poles into corresponding discrete-time poles

using bilinear transformation is nonlinear and becomes significantly different

for high frequency poles and zeros. However, this highly nonlinear mapping of

the high frequencies in equation (3.1) can be corrected by applying a frequency

pre-wrapping scheme before the bilinear transformation. This method replaces

each s in the analog transfer function with
ω
w
p
s,whereω
0
is the frequency to

be matched in the digital transfer function and

T
tan
ω
0
T

2

ω
p
=

.

2

Such a mapping provides the matching of a single critical frequency between the

analog domain and the digital domain. Bilinear transformation with frequency

pre-wrapping provides a close approximation to the analog compensator and

is widely used in practice.

An alternative discretization method is the matched pole-zero or matched

z-transform. This method maps all poles and zeros of the compensator transfer

function from the s-plane to the z-plane according to the relation

z = e
sT

(3.2)

where T is the sampling period. If there are more poles than zeros, additional

zeros are added at z = −1. Also, the gain of the digital filter is adjusted to

match the gain of the analog filter at some critical frequency such as the DC