Digital Signal Processing Reference
In-Depth Information
V
stab
V
stab
V
in
,DC
V
in
,DC
V
in
,DC
V
in,p
V
out,n
1
3
9
V
in,n
V
out,p
V
in,DC
V
in,DC
V
in,DC
V
stab
V
stab
Fig. 3.19
Implementation of the presented 3-stage op amp
applied in the BGE load and employs a 34pF capacitor and a 25
m switch
that determines if the op amp is in the precharge phase or in the hold phase.
In order to stabilize the op amp, pole splitting is applied through Miller capacitors
which have a 34pF capacitance. Additionally, feedforward blocking resistors, im-
plemented with 1.5mm/15
µ
m/5
µ
µ
m transistors biased in the linear region, are included.
Contrarily to the high-frequency behavior which is stabilized, the low-frequency be-
havior is not stable in the continuous mode. It requires a precharge phase that resets
the starting conditions for the amplifier.
In the design of this amplifier there are two types of high-pass filters implemented.
•
The high-pass filter that is present in the BGE load,
•
The high-pass filter that is used as a level shifter in between the consecutive stages.
Their different function results in a different effect on the low-frequency behavior of
the amplifier. The high-pass filter in the BGE load introduces a zero-pole doublet in
the amplifier behavior as mentioned in Sect.
3.3.1.4
, hence a simulated 36
◦
bump is
present in the phase characteristics of the amplifier. The placement of three identical
