Digital Signal Processing Reference
In-Depth Information
V
DD
•
The
V
SG
,
3
is limited by
2
whereas the
V
SG
,
2
can not endlessly decrease as
transistors
M
2
must remain biased in the saturation region.
The ratio between
L
•
ratios of
M
2
and
M
3
increases quadratically with the desired
gain.
As the transistors in this work have not been designed with a
L
ratio below 5 due to
modeling issues, the
L
2
increases quadratically with the gain. This dramatically
increases the parasitic gate-drain overlap capacitance
C
gd
,
2
of the input transistor
that behaves like a Miller capacitor. That in turn increases the capacitive load that
is experienced at the inputs of the amplifier and moreover the positive Miller zero
frequency shifts towards lower frequencies and in the signal bandwidth. Simulation
results that compare an amplifier with diode load with other load topologies that are
presented are given in Sect.
3.2.3.5
.
3.2.3.3 Hybrid Load
The hybrid load that is presented in Fig.
3.5
b is a less obvious topology but it is
interesting from a theoretical point of view. This topology is a trade-off between the
zero-
V
GS
load and the diode load. The bias voltage at the gate is now an intermediate
voltage determined by the resistive divider and situated between the source voltage
and the drain voltage. The properties of the hybrid load are all in a direct trade-
off between the diode load with a better reliability and the zero-
V
GS
load with a
higher gain. Depending on the application with this topology either a defensive or
an aggressive balance can be chosen. The drawback of this topology is that it is
built using resistors that are not available in the applied technologies. Moreover this
topology does not meet the specification of high gain combined with high reliability.
Simulation results comparing an amplifier with hybrid loadwith other load topologies
are given in Sect.
3.2.3.5
.
3.2.3.4 Bootstrapped Gain-Enhancement
The zero-
V
GS
load and the diode load each have an important advantage but they fall
short in providing a load topology that scores well on high reliability and high gain
at the same time. The hybrid load enables the trade-off between both advantages but
also fails to combine them. A solution that effectively combines both advantages is
shown in Fig.
3.6
a. The bootstrapped gain-enhancement (BGE) technique employs
a high-pass
RC
filter, implemented as a capacitor
C
and a switch transistor
M
bge
,
together with the p-type load transistor
M
3
. The capacitor
C
is connected to the
source and the gate of
M
3
while the switch connects the gate to
V
SS
. The behavior
of this load is explained by a precharge and a hold phase. When
V
bge
is low in the
precharge phase
C
is charged with
V
out
and the load acts like a diode load. Next in the
hold phase the
V
bge
is high and
C
remains charged. As a result transistor
M
3
is biased
with a high gate overdrive in DC, just like the diode load, hence this load scores well
