Digital Signal Processing Reference
In-Depth Information
(a)
(b)
4
x
10
−6
10
−6
3.5
zerovgs load
3
diode load
2.5
diode load
2
10
−8
1.5
zerovgs load
1
0.5
10
−10
0
−5
0
5
10
15
−5
0
5
10
15
V
SG
[V]
V
SG
[V]
Fig. 3.4
The
V
SG
V
T
of 1V
(
gray
)
a
on a linear scale and
b
on a logarithmic scale. The
arrows
point at the effect on the transistor
current when the transistor is biased with
V
SG
−
I
SD
curve of an organic transistor and the same curve after a
±
=
0 V (zero-
V
GS
load) and with
V
SG
=
V
DD
/
2
=
7.5
V (diode load)
where
V
E
is the Early voltage of the transistor. The impedance
r
sd
is only influenced
by
V
SG
−
V
T
through the current
I
sd
. Consequently, since gain is independent of the
current, the gain of the amplifier is stable and high. If so desired the output resistance
of the transistor can be further increased by increasing
L
and keeping the
W
/
L
ratio
constant.
Although the zero-
V
GS
load topology scores well for high gain, its behavior is not
very reliable. In this topology the gate contact and the source contact are connected,
so
V
SG
is. The generic
V
SG
−
I
SD
curve of an organic transistor is presented in
Fig.
3.4
, both in the linear and the logarithmic scale. The gray lines on the curve
represent the initial curve that has undergone a shift of the threshold voltage
±
V
T
.
The effect of
V
T
on the current through the zero-
V
GS
transistor is large and on
the logarithmic plot it is visible that a
±
V
T
of 1 V can even influence the current
by a factor of almost 2. Digital gates are mostly affected by this change in terms
of speed, but the proper functionality will remain as long as the gain of the stage
remains higher than 1. For analog circuits, such as the differential amplifier, such
a
V
T
change is very adverse for the DC bias levels and a fast degradation of the
functionality would occur.
Next to the important case of the
±
V
T
change, also the mismatch between the load
transistor currents plays an important role in the differential amplifier, i.e. mismatch
results in output offset and disturbs the differential output signal of the amplifier.
The mismatch in this load topology is therefore a second reason why this zero-
V
GS
load performs poorly. Simulation results of a differential amplifier with this load type
employed are given and compared to the simulation results of the other topologies
in Sect.
3.2.3.5
.
