Digital Signal Processing Reference
In-Depth Information
Diode
Enhanced Diode
V
+Δ
V
V
V
+Δ
V
V
out
out
out
out
S
D
S
D
G
G
V
−V
2
out
DD
V
+V
DD
out
G
G
2
ou
V−
DD
V
ou
V−
DD
V
out
out
S
D
S
D
Fig. 6.20
Schematic view with bias levels of switch
S
4
,
h
implemented as a diode or as a diode
enhanced with a high-pass filter, both in its on-state (
forwardly biased
) and in its off-state (
reversely
biased
)
in each Dickson stage is 4pF compared to 2pF. This actually doubles the expected
output current of the converter while the output voltage is expected to be more or
less the same. The equation below (
6.11
) estimates the efficiency
η
3
of this design
as a function of
η
2
, the efficiency of design 2.
P
out
,
3
P
clk
,
3
=
2
·
P
out
,
2
η
3
≈
P
clk
,
2
=
5
.
2
·
η
2
(6.11)
(
1
−
0
.
62
)
·
where
P
out
,
i
and
P
clk
,
i
are respectively the output power and the power consumption
for the clock circuitry in the converter design i. From this reasoning an efficiency
increase with a factor 5
.
2 is expected for this design.
6.3.3.3 Measurement Results
The measured output voltage characteristics are presented in Fig.
6.21
. The converter
reaches output voltages of
36V for a power supply voltage of 20Vwhile
the ring oscillator and the buffers consume 1.4
+
47V and
−
A. The converter performs with a
clock speed of 660Hz. When a 10nA output current is drawn the high output voltage
V
out
,
h
lowers to 40V. According to equation (
6.11
) the converter efficiency
µ
η
3
is
1
4%fora20V
V
DD
and a 10nA output current. The working point in which this
efficiency is calculated is very similar to that used in
6.3.2.3
and the efficiency has
increased by a factor of 1
.
.
5. Themeasurement results of the converter are summarized
in Table
6.8
. The chip photograph is shown in Fig.
6.22
.
