Digital Signal Processing Reference
In-Depth Information
inverted clock signals and can be easily implemented as an inverter driven by a single
clock signal.
Although the passive implementation of
S
1
,
i
and
S
4
is the easiest implementation
for these switches, they behave far from ideally.
Firstly, a transistor in the applied organic electronics technology is not yet fully
switched off when
V
SG
is 0V since the threshold voltage is close to 0V. Therefore
the off-current
I
of f
is not very low and the
I
on
/
I
of f
ratio is significantly reduced.
Furthermore this ratio is very sensitive to
V
T
variation and
V
T
shift, since the current
in sub-threshold changes logarithmically with
V
SG
.
Secondly, the
V
SD
of the transistor during the
of f
state is large, around 2
V
DD
,
which also has a small but negative influence on the
I
of f
and therefore on the
I
on
/
.
I
of f
ratio.
Thirdly, when the transistor is in the
on
-state after settling, all of its nodes are at
the same voltage level, hence the transistor does not draw any current. During the
evolution towards this final state the transistor biasing becomes worse and the
R
on
becomes higher slowing down the settling. This introduces a trade-off between clock
speed and output voltage.
The clock signal is generated on the chip by the 9-stage ring oscillator im-
plemented with inverters that each have a 140
µ
µ
m/3
m pull-up transistor and a
1,400
m zero-
V
GS
load transistor. In order to drive the capacitors at nodes
n
4
and
n
5
the clock signal is buffered with a chain of five sized inverters. The finger
width of all the transistors in the ring oscillator and the buffer is reduced from the
safer 5
µ
m/3
µ
m in order to reduce the gate-source (
C
gs
) and gate-drain
(
C
gd
) capacitors with 40%. Therefore the clock speed increases with an estimated
67%.
µ
m towards 3
µ
6.3.1.2 Simulation
The behavior of the converter is simulated based on measurements of single transis-
tors that are processed in the same technology. The simulated behavior of the Dickson
converter with a varying power supply voltage is shown in Fig.
6.12
a. The output
voltage of 48V is reached with a 15V power supply and goes up to 88V for a 25V
supply. The simulated clock frequency is 500kHz, which is likely an overestimation
since the simulation is done with extracted information from earlier transistor mea-
surements and with a capacitive transistor model that poorly fits to the technology.
The second curve is the simulated behavior when a load current of 10
A is applied.
Now the output voltage is lowered by 6V and the output resistance of the converter
is estimated as 0.6M
µ
.
Figure
6.12
b shows the simulated behavior of nodes
n
1
−
3
together with the output
voltage in steady-state behavior. The charging principle of this converter, discussed
in Sect.
6.2.3.4
, is now visualized. Node
n
1
is charged by
V
DD
during
φ
1
and then
charges
n
2
during
φ
2
. Node
n
2
for his part charges
n
3
during
φ
1
and consequently
the output node
n
out
is charged by
n
3
during
φ
2
. The voltage loss, while one node
