Digital Signal Processing Reference
In-Depth Information
φ
1
φ
φ
1
φ
2
2
n
1
n
n
n
out
V
out
V
DD
2
3
S
1,1
S
S
1,3
S
1,2
4
C
1
C
C
φ
2
2
3
V
DD
n
4
C
out
R
L
φ
1
S
V
DD
n
5
3,1
φ
1
S
S
2,1
3,2
φ
S
2,2
2
V
SS
(a)
n
1
n
2
n
3
n
1
n
2
n
3
n
out
V
out
n
out
V
out
V
DD
V
DD
C
C
1
C
3
2
C
out
C
out
C
1
C
3
R
L
C
2
R
L
V
DD
V
DD
V
DD
V
SS
V
SS
(b)
(c)
Fig. 6.10
a
Schematic of the ideal 3-stage Dickson up-converter.
b
The schematic during
φ
1
.
c
The schematic during
φ
2
Table 6.5
Comparative overview of the implementation details of switches in the series-parallel,
the voltage-doubler, the Fibonacci and the Dickson architectures. The required number of each type
of switch is given. The total number of switches and the total number of clock signals needed are
also included
Passive
DC bias
Clocked
Clocked
#
S
i
#Clock
voltage
V
DD
>
V
DD
signals
3-st. Series-Parallel
4
2
2
2
10
4
2-st. Voltage doubler
4
0
4
0
8
4
3-st. Fibonacci
4
0
2
4
10
6
3-st. Dickson
4
0
2
0
8
2
6.2.3.5 Discussion
Table
6.5
summarizes the implementation of the series-parallel, the voltage-doubler,
the Fibonacci and the Dickson architectures. The Fibonacci converter needs six
additional clock signals, four of which must be above the supply voltage. Therefore
this topology is not of interest. The series-parallel converter scores slightly better with
only four additional clock signals, two of which must be above the supply voltage.
The voltage doubler and the Dickson architectures only require clock signals that
can easily be generated with the available voltage levels and perform almost equally.
However, the Dickson converter only requires two of these signals, whereas the
voltage doubler requires four of these. An interesting feature of the Dickson topology
is that it only uses eight switches in a 3-stage converter whereas the other 3-stage
