Digital Signal Processing Reference
In-Depth Information
Table 6.2
Overview of the implementation details of switches in the 3-stage series-parallel topol-
ogy. The required number of each type of switch is given. The total number of switches and the
total number of clock signals needed are also included
Passive
DC bias
Clocked
Clocked
#
S
i
#Clock
voltage
V
DD
>
V
DD
signals
3-st. Series-Parallel
4
2
2
2
10
4
φ
1
they are all biased with
V
DD
at
their left plate and with
V
SS
at their right plate. During that phase
S
3
,
i
may not draw
current hence a bias voltage of
V
DD
or higher is required. During
Switches
S
3
,
i
are closed during
φ
2
.During
φ
2
both plates of
V
DD
. Except for
S
3
,
1
,all
S
3
,
i
can be switched by a DC
voltage
V
DD
or slightly higher. These switches are of no cost for the implementation
of this converter. Switch
S
3
,
1
cannot be biased with a DC voltage. Nevertheless, it
can be biased pretty easily with a standard clock signal between
V
DD
and
V
SS
and
does not present a problem for the implementation.
Finally switch
S
4
is in a very similar situation to switches
S
1
,
i
and can be imple-
mented in the same way, i.e. passively with a diode-connected transistor.
The conclusion is that most of the switches, i.e.
S
1
,
i
,
S
3
,
i
and
S
4
, can be easily
implemented. However, switches
S
2
,
i
make the implementation of this topology
very difficult since they require high swing switching signals at voltage levels far
beyond
V
DD
. Table
6.2
summarizes the numbers of switches of different types and
the number of clock signals needed for this topology.
S
3
,
i
are at the same voltage
i
.
6.2.3.2 Voltage Doubler Architecture
The schematic of a single-stage voltage doubler is similar to that of the series-
parallel architecture in Fig.
6.6
and, as a result, the same working principle applies.
The difference between the voltage doubler and the series-parallel architecture lies
in the connection between consecutive stages. Figure
6.8
a shows a 2-stage voltage
doubler architecture. In the circuit a capacitor
C
o
1
is present that stores the 2
V
DD
output of the first stage at node
n
o
1
. This DC voltage is then used as the input voltage
for the subsequent voltage doubler. The output voltage
V
out
at
n
out
has an ideal value
of 4
.
φ
2
are visualized
in Figs.
6.8
b and
6.8
c. More generally the output of an
n
th order voltage doubler
is 2
n
. This topology reaches the same output voltage as the series-parallel topology
with only two instead of three stages. Please note that this topology applies two more
capacitors that must be large to reduce the output ripple.
The switches in a voltage doubler behave very comparablywith those in the series-
parallel converter, discussed in
6.2.3.1
. Switch
S
1
,
1
must conduct forward current
while both its pins are at a voltage
V
DD
and must not draw backward current when
node
n
1
is at 2
.
V
DD
. The charging principles of this converter during
φ
1
and
.
V
DD
.
S
4
,
1
must block backwards current when
n
1
is at
V
DD
and
