Digital Signal Processing Reference
In-Depth Information
φ
1
φ
2
V
out
V
DD
S
1
S
2
C
1
φ
1
C
2
R
L
S
4
S
3
φ
2
V
SS
(a)
V
DD
V
DD
V
out
C
1
V
out
R
L
C
1
C
2
C
2
R
L
V
SS
V
SS
(b)
(c)
Fig. 6.2
a
A capacitive series-parallel down-converter.
b
The converter in phase
φ
1
.
c
The converter
in phase
φ
2
6.2.1.1 Down-Converters
DC-DC down-converters apply reactive components, either capacitors or inductors,
in a schematic with switches for creating their outputs. By connecting the reactive
components in different positions an output power
P
out
is produced at an output
voltage
V
out
. Figure
6.2
gives the example of a capacitive series-parallel down-
converter that generates an output voltage of
V
DD
/
φ
1
the capacitors
are connected in series through switches
S
1
and
S
4
and they are charged to
V
DD
/
2. In clock phase
2
each by the supply voltage
V
DD
. In clock phase
φ
2
the capacitors are connected
in parallel through switches
S
2
and
S
3
. They are both still charged to
V
DD
/
2 and
provide this voltage to the output of the converter.
The conversion ratio
k
out
is defined in equation (
6.1
). For down-converters this
ratio is always between 0 and 1. The power efficiency
η
P
for a certain output voltage
is defined by equation (
6.2
) where
P
tot
is the total power dissipated in the circuit and
P
int
the internally dissipated power.
V
out
V
DD
k
out
=
(6.1)
