Digital Signal Processing Reference
In-Depth Information
(a)
0
(b)
30
signal
int. noise
int. noise + dist
SNR
SNDR
−10
25
−20
SNR = 26.50 dB
SNDR = 26.50 dB
20
−30
15
−40
10
−50
5
−60
−70
0
10 −1
10 0
10 1
10 2
0.1
0.2
0.4
1
2
4
Input Amplitude [V]
Frequency [Hz]
Fig. 4.12
ADC with a
2V rmptp 10Hz sinusoidal input and a 500Hz clock frequency. b The measured SNR and SNDR
for a 3Hz input with a varying amplitude at a 500Hz clock frequency
a Measured output power spectral density of the presented 1 st -order
the measured SNR and SNDR of the ADC are visualized versus the input amplitude
of a 3Hz input signal. In this figure the linear relation between input amplitude and
SNR/SNDR is clearly visible. The peak SNR for 3Hz input is 25dB. The 1dB loss,
compared to the SNR for a 10Hz input, is probably caused by the high-pass filters
in the circuit. A difference between SNR and SNDR of about 3dB is present, even
for low amplitudes. This might be caused by distortion in the analog filter or in the
feedback circuit. The circuit consumes 100
m from a 15V power supply. Table 4.1
summarizes the measurement results. The chip photograph of the presented circuit
is shown in Fig. 4.13 .
Due to the high-pass filters in the single-stage amplifiers and in the throughput
between consecutive stages there is not enough phase margin for low frequencies.
This means that the continuous-time behavior of this circuit is unstable at frequencies
around 0.1-1Hz. A precharge-and-hold functionality, as discussed in Sect. 3.3.2.1 ,
is therefore applied during these measurements, which are then performed in the
hold phase. The 2 nd -order ADC is even more unstable for low frequencies due
to the higher number of low-frequency poles in the 2 nd -order analog filter. As a
consequence the frequency of the oscillation becomes higher and the hold phase
in the precharge-and-hold measurement setup is not long enough to carry out the
measurements.
µ
4.4 Discussion
As outlined in Sect. 4.3.6 the high-pass filters in the presented designs cause unsta-
ble behavior at low frequencies. In the 1 st -order ADC the problem was overcome
through a precharge-and-hold way of measuring and good measurements have been
performed whereas in the 2 nd -order architecture even with this technique it has
 
 
Search WWH ::




Custom Search