Digital Signal Processing Reference
In-Depth Information
15
14
13
12
11
10
9
8
7
0
1
2
3
4
5
Time [ms]
Fig. 4.9
Measured differential output of the presented latch
V
filt
V
h
M
1,a
M
1,b
V
in,p
Component
Size
C
filt
M
1
10 mm/5 µm
M
filt,a
V
out,n
V
out,p
M
2
10 mm/5 µm
V
1
M
filt
140 µm/130 µm
C
filt
M
filt,b
C
filt
34 pF
V
in,n
M
2,a
M
2,b
V
l
Fig. 4.10
Implementation of the level shifter and a list of the transistor sizes
Finally, in the third place, this level shifter has a buffer functionality that can drive
the TL084 op amp which is connected in unity-feedback configuration and reads out
the chip output on the test setup.
The implementation of the level shifter is shown in Fig.
4.10
. The two inverters,
which are differentially driven, make the output signals switch between the desired
digital levels,
V
l
and
V
h
. Two high-pass filters ensure that the switching signals
are brought to the appropriate level
V
1
. Since the input swing is larger than the
output swing the level shifter improves the digital character of the output signals.
This circuit has not been separately measured because its complexity is low and its
behavior straightforward.
