Information Technology Reference
In-Depth Information
Architectural support for fast mode switches
Some processor architectures are able to execute user and kernel mode switches
very efficiently, while other architectures are much slower at performing these switches.
The SPARC architecture is in the first camp. SPARC defines a set of register windows
that operate like a hardware stack. Each register window includes a full set of the reg-
isters defined by the SPARC instruction set. When the processor performs a procedure
call, it shifts to a new window, so the compiler never needs to save and restore registers
across procedure calls, making them quite fast. (At a deep enough level of recursion,
the SPARC will run out of its register windows; it then takes an kernel exception that
saves half the windows and resumes execution. Another exception is taken when the
processor pops its last window, allowing the kernel to reload the saved windows.)
Mode switches can be quite fast on the SPARC. On a mode switch, the processor
switches to a different register window. The kernel handler can then run, using the
registers from the new window and not disturbing the values stored in the interrupted
process's copy of its registers. Unfortunately, this comes at a cost: switching between
different processes is quite expensive on the SPARC, as the kernel needs to save and
restore the entire register set of every active window.
The Motorola 88000 was in the second camp. The 88000 was an early pipelined
architecture; for improved performance, multiple instructions were in various stages of
execution at the same time. For example, one instruction might be fetching the instruc-
tion while another is doing a floating point operation and yet another is finishing a store
to memory. When an interrupt or exception occurred on the 88000, the pipeline opera-
tion was suspended, and the operating system kernel was required to save and restore
the entire state of the pipeline to preserve transparency.
Most modern processors with deep execution pipelines, such as the x86, in-
stead provide precise interrupts: in hardware, all instructions that occur be-
fore the interrupt or exception, according to the program execution, are com-
pleted by the hardware before the interrupt handler is invoked. Any instruc-
tion is annulled if it occurs in the program after the interrupt or exception,
even if the instruction is in progress when the processor detects the exception.
