The Kernel Abstraction - Operating Systems: Principles and Practice - page 73

registers.
Putting it all together: Mode switch on the x86
As noted above, the high level steps needed to handle an interrupt, trap, or
exception are simple, but the details require some care.
To give a concrete example of how such \carefully crafted" code works, we
now describe one way to implement interrupt-triggered context switch on the x86
architecture. Different operating systems on the x86 follow this basic approach,
though details differ. Similarly, different architectures handle the same types of
issues, but they may do so with different hardware support.
First, a bit of background on the x86 architecture. The x86 is segmented,
and so pointers come in two parts: a segment, such as code, data or stack,
and an offset within that segment. The current user-level instruction is based
on a combination of the code segment ( cs register plus the instruction pointer
eip ). Likewise, the current stack position is based on the stack segment ss and
the stack pointer within the stack segment esp . The current privilege level is
stored as the low order bits in the cs register, rather than the processor status
word eflags . The eflags register has condition codes that are modified as a
by-product of executing instructions; the eflags register also has other flags
that control the processor's behavior such as whether interrupts are masked or
not.
When a user-level process is running, the current state of the processor,
stack, and kernel interrupt vector and kernel stack is illustrated in Figure 2.9.
When an exception or trap occurs, the hardware carefully saves a small amount
of the interrupted thread state, as illustrated in Figure 2.10:
1. Save three key values. The hardware internally saves the value of
the stack pointer (the x86 esp and ss registers), the execution flags (the
x86 eflags register), and the instruction pointer (the x86 eip and cs
registers).
2. Switch onto the kernel exception stack. The hardware then switches
the stack pointer to the base of the kernel exception stack, specified in a
special hardware register.
3. Push the three key values onto the new stack. The hardware then
stores the internally saved values onto the stack.
4. Optionally save error code. Certain types of exceptions such as page
faults generate an error code to provide more information about the event;
for these exceptions, the hardware pushes this code as the last item on the
stack. For other types of events, the software interrupt handler typically
pushes a dummy value onto the stack so that the stack format is identical
in both cases.