Fabrication of thin-film transistors on polyimide films - Polyimides and Other High Temperature Polymers - page 459

3. EXPERIMENTS

We fabricated amorphous silicon (a-Si:H) thin-film transistors (TFTs) at 150ºC on
free-standing Kapton E substrates passivated on both sides with SiN x deposited by
plasma enhanced chemical vapor deposition (PECVD) [22]. The standard a-Si:H
TFT process temperatures lie between 250ºC and 350ºC. We have reduced the
temperature to 150ºC [23] for two reasons: (i) several other polymers can with-
stand the temperature of 150ºC [24] and therefore a 150ºC TFT technology can be
used on other substrates, and (ii) a-Si:H and SiN x layers grown by PECVD at
150ºC can be grown with a quality comparable to the materials grown at the stan-
dard temperature [23].
It is known that the quality of the amorphous silicon (a-Si:H) and silicon nitride
(SiN x ) deposited by PECVD deteriorates with decreasing deposition temperature.
During growth at 150 C, the usual source gases are diluted with hydrogen to as-

sure that the electronic properties of a-Si:H and SiN x layers are comparable to
those of a-Si:H / SiN x grown at the optimum temperature of 250-350

°

C [23].
Figure 1 shows a schematic cross section of substrate and thin-film transistor.
The TFTs have the inverted, bottom gate staggered geometry with SiN x back-
channel passivation. The polyimide substrate foil was first coated on both sides
with a 0.5 µm thick layer of SiN x . All TFTs had the following structure: ~ 100 nm
thick Ti/Cr layer as gate electrode, ~ 360 nm of SiN x as gate dielectric, ~ 100 nm
of undoped a-Si:H as channel material, 180 nm of passivating SiN x , ~ 50 nm of
highly phosphorus-doped (n + ) a-Si:H, and ~ 100 nm thick Al for the source-drain
contacts. The TFT channel length was 40 µm and channel width was 400 µm.
Fabrication details are given elsewhere [23]. The stress was balanced between the
TFT layers such that the foil was flat after fabrication, as shown in Fig. 2(a). Fig-
ure 2(b) demonstrates the flexibility of the 75 x 75 mm Kapton substrate bearing
100 a-Si:H TFTs. We have studied the stability of these TFTs under dc electrical
bias [25] and carried out extensive experimental and theoretical studies of the
bending of TFTs on thin foils [26, 27].

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Figure 1. Cross-sectional view of the a-Si:H thin-film transistor showing layer materials and thick-
nesses.