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[Lee 2005] Lee, E.: Absolutely, positively on time: What would it take? IEEE Computer, 85-87
(2005)
[Godefroid et al 2005] Godefroid, P., Klarlund, N., Sen, K.: DART: Directed Automated Ran-
dom Testing. In: Proc. ACM PLDI, Chicago, pp. 213-223 (2005)
[Godefroid 2007] Godefroid, P.: Compositional dynamic test generation. In: Proc. ACM POPL,
Nice, pp. 47-54 (2007)
[Joseph 2007] Joseph, M.: Abstractions for real-time systems. In: Proc. TASE, p. 22 (2007)
[Cook et al 2007] Cook, B., Podelski, A., Rybalchenko, A.: Proving thread termination. In: Proc.
ACM PLDI, San Diego (2007)
[Cook et al 2006] Cook, B., Podelski, A., Rybalchenko, A.: Termination proofs for systems
code. In: Proc. ACM PLDI, Ottawa, pp. 415-426 (2006)
[Henzinger & Sifakis 2006] Henzinger, T.A., Sifakis, J.: The embedded systems design chal-
lenge. Invited paper, Formal Methods (2006)
[Henzinger et al 1991] Henzinger, T.A., Manna, Z., Pnueli, A.: Temporal proof methodologies
for timed transition systems. Inf. & Control 112(2), 273-337
[Marasco 2006] Marasco, J.: Software development productivity and project suc-
cess rates: are we attacking the right problem?
http://www-128.ibm.com/
[Sukumaran et al 2006] Sukumaran, S., Sreenivas, A., Venkatesh, R.: A rigorous approach to
requirements Validation. In: Proc. SEFM 2006, IEEE Press, Los Alamitos (2006)
[Agrawal et al 2006] Agrawal, M., Stephan, F., Thiagarajan, P.S., Yang, S.: Behavioural approx-
imations for restricted linear differential hybrid automata. In: Hespanha, J.P., Tiwari, A. (eds.)
HSCC 2006. LNCS, vol. 3927, pp. 1-18. Springer, Heidelberg (2006)
[Agrawal & Thiagarajan 2005] Agrawal, M., Thiagarajan, P.S.: The discrete time behaviour
of lazy linear hybrid automata. In: Hespanha, J.P., Tiwari, A. (eds.) HSCC 2006. LNCS,
vol. 3927, pp. 1-18. Springer, Heidelberg (2006)
[Stankovic et al 2005] Stankovic, J.A., Lee, I., Mok, A., Rajkumar, R.: Opportunities and oblig-
ations for physical computing systems. IEEE Computer, 23-31 (November 2005)
[Sharma et al 2006] Sharma, B., Pandya, P., Chakraborty, S.: Bounded validity checking of in-
terval duration logic. In: Kalviainen, H., Parkkinen, J., Kaarna, A. (eds.) SCIA 2005. LNCS,
vol. 3540, pp. 301-316. Springer, Heidelberg (2005)
[Chakravorty & Pandya 2003] Chakravorty, G., Pandya, P.: Digitizing interval duration logic. In:
Proc. CAV, Boulder, pp. 167-179 (2003)
[Pandya et al 2007] Pandya, P., Krishna, S.N., Loya, K.: On sampling abstraction of continuous
time logic with durations. In: Grumberg, O., Huth, M. (eds.) TACAS 2007. LNCS, vol. 4424,
pp. 246-260. Springer, Heidelberg (2007)
[Liu & Layland 1973] Liu, C.L., Layland, J.: Scheduling algorithms for multiprogramming in a
hard-real-time environment. J. ACM 20(1), 46-61 (1973)
[Gossler & Sifakis 2000] G ossler, G., Sifakis, J.: Priority Systems. In: de Boer, F.S., Bonsangue,
M.M., Graf, S., de Roever, W.-P. (eds.) FMCO 2003. LNCS, vol. 3188, pp. 314-329. Springer,
Heidelberg (2004)
[Henzinger et al 2003] Henzinger, T., Kirsch, C.M., Sanvido, M.A.A., Pree, W.: From control
models to real time codes using Giotto. IEEE Contr.SYS., February, 50-64
[Joseph & Pandya 1986] Joseph, M., Pandya, P.K.: Finding response times in a real-time system.
Comp.J., 29(5), 390-395.
[Warneke et al 2002] Warneke, B., Last, M., Liebovitz, B., Pister, K.S.J.: Smart dust: communi-
cating with a cubic millimetre computer. IEEE Computer, 44-51 (2001)
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