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15. Schaumont, P., Ching, D.: GEZEL version 2 (2006),
16. Thomas, D.E., Moorby, P.R.: The Verilog Hardware Description Language. Kluwer
Academic Publishers, Dordrecht (1998)
17. Stein, J.: Journal of Computational Physics 1(3), 397-405 (1967)
18. IEEE Standard VHDL Language Reference Manual, IEEE Std 1076-2000 (2000)
A
Gezel Specification of a gcd-Algorithm
dp gcd(in a, b : ns(8);
out c : ns(8)) {
reg x, y, factor : ns(8);
reg done
: ns(1);
sfg init { x = a; y = b; factor = 0; done = 0; c = 0; }
sfg shiftx { x = m >> 1; }
sfg shifty { y = n >> 1; }
sfg reduce { x = (x >= y) ? x - y : x;
y=(y> x)?y-x:y;}
sfg shiftf { factor = factor + 1; }
sfg outidle { c = 0; done = ((x == 0) | (y == 0)); }
sfg complete{ c = ((x > y) ? x : y) << factor; }
}
fsm gcd_ctl(gcd) {
initial s0;
state s1, final;
@s0 (init, outidle) -> s1;
@s1 if (done)
then (complete)
-> final;
else if ( x[0] & y[0]) then (reduce, outidle)
-> s1;
else if ( x[0] & ~y[0]) then (shifty, outidle)
-> s1;
else if (~x[0] & y[0]) then (shiftx, outidle)
-> s1;
else (shifty, shiftx,
shiftf, outidle)
-> s1;
@final (outidle) -> final;
}
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