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bus.address # arg(IR);
state !! ;
case EXEC_STOREB:
if (bus.command.equals(RAM.ACK))
state # FETCH_entry;
break ;
case EXEC_MOVEAB_entry:
bus.command # RAM.RAM_WRITE;
bus.data # RegA;
bus.address # Integer.parseInt(RegB);
state !! ;
case EXEC_MOVEAB:
if (bus.command.equals(RAM.ACK))
state # FETCH_entry;
break ;
case EXEC_ADD_entry:
RegA # Integer.toString(Integer.parseInt
(RegA) ! Integer.parseInt(RegB)); state !! ;
case EXEC_ADD:
state # FETCH_entry;
break ;
}
}
5.5.4
Test
We can identify two different test cases. The first is a sort of regression test;
we want to be able to implement the functionality of the hard-wired program
developed in the previous phase using the CPU instructions. The second is a
more complex test that exercises the features of all the instructions in the
instruction set.
Sum program
The program shown in Table 5.4 sums the contents of memory locations 5
and 6, and puts the result into memory location 6. The difference between
this program and the hard-wired program executed by the CPU in the
previous phase lies in the location used to store data: here we cannot use
location 0 since it must contain the first instruction that is executed by
the CPU.
Test program 2
The program shown in Table 5.5 consists of a loop that fills memory loca-
tions from 20 to 31 with a fixed value (99). This program is structured as a
“for” loop. Instructions 0 and 1 check the loop termination condition
 
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