The read and write operations are based on a command-acknowledge
protocol. First the CPU issues a command, then it waits for the RAM to
perform the operation; the RAM notifies the CPU that the operation has been
completed by issuing an acknowledge message.
In particular, the read operation involves the following steps:
1 The CPU writes the address of the cell to be read on the address bus and
writes the read command on the command bus.
2 The RAM senses the read command on the command bus, takes the cell
address from the address bus, writes the cell content on the data bus, and
writes the acknowledge message on the command bus.
3 The CPU senses the acknowledge message on the command bus and reads
the content of the cell from the data bus.
The write operation is similar and involves the following steps:
1 The CPU writes the address of the destination cell on the address bus, the
content on the data bus, and the write command on the command bus.
2 The RAM finds the write command on the command bus, takes the cell
address from the address bus, reads the content from the data bus, writes
it into the memory cell, and writes the acknowledge message on the
3 The CPU finds the acknowledge on the command bus.
This latter step of the write operation is required to avoid the possibility
that the CPU changes the information on the bus before the RAM has read it.
How do we describe the CPU behaviour?
In this prototype we develop a CPU that executes a fixed program, in par-
ticular we consider a simple program that loads two numbers from the RAM
(cell 0 and cell 1) into the CPU registries (register A and register B), sums
their values, and writes the result into the RAM (cell 2). The operations
performed by the CPU to execute this program are the following:
1 Read RAM cell 0 into register A.
2 Read RAM cell 1 into register B.
3 Sum A and B, and put the result into register A.
4 Write register A into RAM cell 2.
5 Go to HALT state.
The behaviour of the CPU can be described by means of the state machine
shown in Figure 5.7. Operation 1 is carried on in states READ_MEM0 and
READ_A ; operation 2 is carried on in states READ_MEM1 and READ_B ;
operation 3 is performed in state ADD ; operation 4 is carried on in states
WRITE_MEM2 and HALT .