Java Reference
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Domain models
The theory behind computer architectures is quite well understood (see, for
instance, Hayes (1998)). The common structure for a computer is depicted
in Figure 5.2. This is a more detailed description than the one provided in
Figure 5.1.
The CPU is made up of the arithmetic logic unit (ALU) that executes
elemental operations on byte data and the following set of registers to store
operands, results, data and instructions:
A and B: general-purpose registers;
PC, program counter;
IR, instruction register: holds the current instruction.
The general-purpose registers are used to hold information; their contents
can be loaded from and stored to the RAM. They can be manipulated directly
by instructions. The program counter register holds the location of the next
instruction to be executed. It can be modified indirectly by means of jump
instructions. The instruction register (IR) contains the instruction that is
currently being executed.
The behaviour of the CPU can be described by means of a finite state
automaton (FSA). A simple CPU behaves as described in Figure 5.3. The
CPU elaborates each instruction of the assembler-like program following a
three-step process:
Fetch. The CPU copies the next instruction into the instruction register
from the memory location indicated by the PC register.
Decode. The CPU examines the IR and identifies the instruction to be
Execute. The CPU executes the operations required by the decoded
In addition, the CPU has a HALT state that indicates that the execution is
Instruction 1
Instruction n
Figure 5.3 Finite state machine for the CPU
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